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PDF AKD5701 Data sheet ( Hoja de datos )
| Número de pieza | AKD5701 | |
| Descripción | 16-Bit Stereo ADC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AK5701]
AK5701
16-Bit ΔΣ Stereo ADC with PLL & MIC-AMP
GENERAL DESCRIPTION
The AK5701 features a 16-bit stereo ADC. Input circuits include a Microphone-Amplifier and an ALC
(Auto Level Control) circuit that is suitable for portable application with recording function. On-chip PLL
supports base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5701 is
available in a 24pin QFN, utilizing less board space than competitive offerings.
www.DataSheet4U.com
FEATURES
1. Resolution: 16bits
2. Recording Function
- 2 Stereo Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+30dB/+15dB or 0dB)
- Input Voltage: 1.8Vpp@VA=3.0V (= 0.6 x AVDD)
- ADC Performance: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB
S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB
S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
3. Sampling Rate:
- PLL Slave Mode (EXLRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
4. PLL Input Clock:
- MCKI pin:
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s compliment
- DSP Mode, 16bit MSB justified, I2S
7. μP I/F: 3-wire Serial
8. Power Supply:
- AVDD: 2.4 ∼ 3.6V
- DVDD: 1.6 ∼ 3.6V
9. Power Supply Current: 8mA
10. AK5701VN: Ta = −30 ∼ 85°C
AK5701KN: Ta = −40 ∼ 85°C
11. Package: 24pin QFN (4mm x 4mm)
MS0404-E-02
-1-
2007/08
1 page  
[AK5701]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2)
Parameter
Symbol
min
Power Supplies: Analog
AVDD
−0.3
Digital
DVDD
−0.3
|AVSS – DVSS| (Note 3)
ΔGND
-
Input Current, Any Pin Except Supplies
IIN -
Analog Input Voltage (Note 4)
VINA
−0.3
Digital Input Voltage (Note 5)
VIND
−0.3
Ambient Temperature
AK5701VN
Ta
−30
(powered applied)
AK5701KN
Ta
−40
Storage Temperature
www.DataSheet4U.com
Tstg −65
Note 2. All voltages with respect to ground.
Note 3. AVSS and DVSS must be connected to the same analog ground plane.
Note 4. LIN1/LIN+, RIN1/LIN−, LIN2/RIN−, RIN2/RIN+ pins
Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins
max
4.6
4.6
0.3
±10
AVDD+0.3
DVDD+0.3
85
85
150
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Units
V
V
V
mA
V
V
°C
°C
°C
(AVSS, DVSS=0V; Note 2)
Parameter
Power Supplies Analog
(Note 6) Digital
RECOMMENDED OPERATING CONDITIONS
Symbol
AVDD
DVDD
min typ
2.4 3.0
1.6 3.0
Max
3.6
AVDD
Units
V
V
Note 2. All voltages with respect to ground.
Note 6. The power-up sequence between AVDD and DVDD is not critical. When only AVDD is powered OFF, the power
supply current of DVDD at power-down mode may be increased. DVDD should not be powerd OFF while AVDD
is powered ON.
* AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0404-E-02
-5-
2007/08
5 Page 
[AK5701]
Parameter
Control Interface Timing (CSP pin = “L”)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “↑” (Note 22)
CCLK “↑” to CSN Edge (Note 22)
Control Interface Timing (CSP pin = “H”)
CCLK Period
www.DataSheet4UC.coCmLK
Pulse
Pulse
Width
Width
Low
High
CDTI Setup Time
CDTI Hold Time
CSN “L” Time
CSN Edge to CCLK “↑” (Note 22)
CCLK “↑” to CSN Edge (Note 22)
Power-down & Reset Timing
PDN Pulse Width (Note 23)
PMADL or PMADR “↑” to SDTO valid (Note 24)
HPF1-0 bits = “00”
HPF1-0 bits = “01”
HPF1-0 bits = “10”
Symbol
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tPD
tPDV
tPDV
tPDV
min
142
56
56
28
28
150
50
50
142
56
56
28
28
150
50
50
150
-
-
-
Note 22. CCLK rising edge must not occur at the same time as CSN edge.
Note 23. The AK5701 can be reset by the PDN pin = “L”.
Note 24. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3088
1552
784
max Units
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- 1/fs
- 1/fs
- 1/fs
MS0404-E-02
- 11 -
2007/08
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AKD5701.PDF ] | |
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