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PDF SM8052 Data sheet ( Hoja de datos )
| Número de pieza | SM8052 | |
| Descripción | (SM8051 / SM8052) 8-Bit Micro-controller | |
| Fabricantes | SyncMOS | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SM8052 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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SyncMOS Technologies Inc.
May 2001
Product List
SM8051L25, 25 MHz 4KB internal ROM MCU
SM8052L25, 25 MHz 8KB internal ROM MCU
SM8051C25, 25 MHz 4KB internal ROM MCU
SM8052C25, 25 MHz 8KB internal ROM MCU
SM8051C40, 40 MHz 4KB internal ROM MCU
SM8052C40, 40 MHz 8KB internal ROM MCU
Description
The SM8051/8052 series product is an 8 - bit single chip
micro controller with 4/8 KB ROM embedded. It
provides hardware features and a powerful instruction set,
necessary to make it a versatile and cost effective
controller for those applications demand up to 32 I/O pins
or need up to 4/8 KB ROM memory either for
program or for data or mixed.
Ordering Information
yywwv
SM8051/8052ihhk
yy: year, ww:month
v: version identifier { , A, B, ...}
i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V}
hh: working clock in MHz {25, 40}
k: package type postfix {as below table}
SM8051/80952
8 - Bit Micro-controller
with 4/8KB ROM embedded
Features
Working voltage: 3.0V ~ 3.6V For L Version
4.5V ~ 5.5V For C Version
General 8051/8052 family compatible
12 clocks per machine cycle
4/8 KB internal ROM memory
128/256 bytes data RAM
2/3 16 bit timers/counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instruction
Page free jumps
8-bit unsigned division
8-bit unsigned multiply
BCD arithmetic
Direct addressing
Indirect addressing
Nested interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and power down mode
Code protection function
One watch dog timer (WDT)
Low EMI (inhibit ALE)
Postfix
P
J
Q
Package
40L PDIP
44L PLCC
44L QFP/TQFP
Pin/Pad
Configuration
page 2
page 2
page 2
Dimension
page 13
page 14
page 15/16
Specifications subject to change without notice,contact your sales representatives for the most recent information.
1/16
Taiwan
4F, No. 1 Creation Road 1,
Science-based Industrial Park,
Hsinchu, Taiwan 30077
TEL: 886-3-579-2926
886-3-579-2988
FAX: 886-3-579-2960
886-3-578-0493
Ver 1.1
SM8051/8052 07/2005
1 page  
www.DataSheet4U.com
SyncMOS Technologies Inc.
May 2001
SM8051/8052
SFR Memory MAP
$F8
$F0 B
$E8
$E0 ACC
$D8
$D0 PSW
$C8 T2CON
RC2L
RC2H
TL2
TH2
$C0
$B8
$B0
$A8
$A0
$98
$90
$88
$80
IP
P3
IE
P2
SCON
P1
TCON
P0
SBUF
TMOD
SP
TL0
DPL
TL1
DPH
TH0
(Reserved)
TH1
SCONF
WDTC
PCON
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM8051/8052
$FF
$F7
$EF
$E7
$DF
$D7
$CF
$C7
$BF
$B7
$AF
$A7
$9F
$97
$8F
$87
Extension Function Description
Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT
is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead
loop or runaway. The WDT function can help user software recover form abnormal software condition. The WDT is different
from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing
the WDT counter.
The SM8051/8052 WDT has selectable divider input for the time base source clock. To select the divider input, the setting
of bit2~bit0 (PS2~PS0) OF Watch Dog Timer Control Register (WDTC) should be set accordingly.
To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to
count with the selected time base source clock which set by PS2~PS0. It will generate a reset signal when overflows. The
WDTE bit will be cleared to 0 automatically when SM8051/8052 been reset, either hardware reset or WDT reset.
To reset the WDT is done by setting 1 to the bit 5 (CLEAR) of WDTC. This will clear the content of the 16-bit counter and let
the counter re-start to count from the beginning.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
5/16
Ver 1.1
SM8051/8052 07/2005
5 Page 
www.DataSheet4U.com
SyncMOS Technologies Inc.
May 2001
SM8051/80952
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12
T1 T2
T3 T4
T5 T6
T7 T8
X1
inputs P0,P1
inputs P2,P3
Output by
Mov Px,Src
RxD at Serial Port
Shift Clock
(Mode 0)
sampled
sampled
current data
sampled
next data
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
Vdd-0.5V
70%Vdd
TCLCL
0.45V
20%Vdd-0.1V
TCHCL
TCLCX
Tm.I External Program Memory Read Cycle
#PSEN
TPLPH
TCLCH
TCHCX
ALE
PORT 0
PORT 2
TLHLL
TAVLL
TLLPL
TLLAX TPLAZ
A0 - A7
TAVIV
A8 - A15
TPLIV
TPXIZ
TPXIX
Instruction. IN
A0 - A7
A8 - A15
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/16
Ver 1.1
SM8051/8052 07/2005
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet SM8052.PDF ] | |
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