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PDF CY7C1471V25 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1471V25 | |
| Descripción | (CY7C147xV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
with NoBL™ Architecture
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero
wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 2.5V/1.8V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard lead-free 100 TQFP, and
165-ball fBGA packages for CY7C1471V25 and
CY7C1473V25. 209-ball fBGA package for
CY7C1475V25.
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect.
• JTAG boundary scan for BGA and fBGA packages
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description[1]
The CY7C1471V25, CY7C1473V25 and CY7C1475V25 are
2.5V, 2M x 36/4M x 18/1M x 72 Synchronous Flow-through
Burst SRAMs designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1471V25, CY7C1473V25 and
CY7C1475V25 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
100 MHz
Maximum Access Time
6.5 8.5
Maximum Operating Current
305 275
Maximum CMOS Standby Current
120 120
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Unit
ns
mA
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05287 Rev. *E
Revised December 5, 2004
1 page  
www.DataSheet4U.com
Pin Configurations (continued)
PRELIMINARY
100-lead TQFP
BYTE B
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1473V25
CY7C1471V25
CY7C1473V25
CY7C1475V25
80 A
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DQPA
73 DQA
72 DQA
71 VSS
70 VDDQ
69 DQA
68 DQA
67
66
VSS
NC
BYTE A
65 VDD
64 ZZ
63 DQA
62 DQA
61 VDDQ
60 VSS
59 DQA
58 DQA
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
Document #: 38-05287 Rev. *E
Page 5 of 30
5 Page 
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PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/Write Abort
(Begin Burst)
Write Abort
(Continue Burst)
Ignore Clock Edge (Stall)
Sleep Mode
Address
Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
None H X X L
L
X X X L L->H Tri-State
None X X H L
L
X X X L L->H Tri-State
None X L X L
L
X X X L L->H Tri-State
None X X X L
H
X X X L L->H Tri-State
External L H L L
L
H X L L L->H Data Out (Q)
Next X X X L
H
X X L L L->H Data Out (Q)
External L H L L
L
H X H L L->H Tri-State
Next X X X L
H
X X H L L->H Tri-State
External L H L L
L
L L X L L->H Data In (D)
Next X X X L
H
X L X L L->H Data In (D)
None L H L L
L
L
HX
L L->H Tri-State
Next X X X L
H
X H X L L->H Tri-State
Current X X X L
None X X X H
X
X
X X X H L->H
-
X X X X X Tri-State
Truth Table for Read/Write[2, 3, 9]
Read
Function (CY7C1471V25)
WE
BWA
BWB
BWC
BWD
HXXXX
Write No bytes written
L HHHH
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
L LHHH
L H L HH
L HH L H
L HHH L
LLLLL
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BWX, and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid Appropriate write will be done based on which byte write is active.
Document #: 38-05287 Rev. *E
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1471V25.PDF ] | |
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