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PDF SH69P25 Data sheet ( Hoja de datos )
| Número de pieza | SH69P25 | |
| Descripción | OTP 4K x 4-Bit Micro-Controller | |
| Fabricantes | Sino Wealth Microelectronic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SH69P25 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SH69P25
PRELIMINARY
OTP 4-bit Microcontroller
Features
SH6610C-based single-chip 4-bit micro-controller
OTPROM: 4096 X 16 bits
RAM: 160 X 4 bits (data memory)
Operation voltage: 2.4V - 6.0V (typical 3.0V or 5.0V)
22 CMOS bi-directional I/O pins
Built in pull-up and pull-low resistor for PortA ~ PortF
4-level subroutine nesting (including interrupts)
One 8-bit auto re-load timer/counter
Warm-up timer for power on reset
Powerful interrupt sources:
- Internal interrupt (Timer0)
- External interrupts: PortB & PortC (rising/falling edge)
Oscillator (OTP option)
- X`tal oscillator:
32.768kHz - 4MHz
- Ceramic resonator: 400k - 4MHz
- RC oscillator:400k - 4MHz
- External clock:
30k - 4MHz
Instruction cycle time:
- 4/32.768kHz(122us) for 32.768kHz OSC clock
- 4/4MHz (1us) for 4MHz OSC clock
Two low power operation modes: HALT and STOP
Built-in watch dog timer (OTP option)
Built-in power on reset
Two LPD level(OTP option)
- High level: 4.0V
- Low level: 2.5V
OTP type &Code protection
General Description
SH69P25 is a 4-bit micro controller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 4K OTPROM, Timer and I/O
Ports.
Pin Configuration
PE2
PE3
PF1
PA2
PA3
T0
RESET
GND
PB0
PB1
PB2
PB3
PD0
PD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 PE1
27 PE0
26 PF0
25 PA1
24 PA0
23 OSCI
22 OSCO
21 VDD
20 PC3
19 PC2
18 PC1
17 PC0
16 PD3
15 PD2
1 V1.01
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SH69P25
3. RAM
The built-in RAM consists of general-purpose data memory and the system register. Direct addressing in one instruction can
access both data memory and the system register.
The following is the memory allocation map:
$000 - $01F: System register and I/O.
$020 - $0BF: Data memory (160 X 4 bits, divided into 2 banks. $020 - $07F: bank0, $080 - $0BF: bank1).
(a) The Configuration of the System Register
Address Bit3 Bit2 Bit1 Bit0 R/W
Remarks
$00 - IET0 -
IEP R/W Interrupt enable flags
$01
- IRQT0 -
IRQP R/W Interrupt request flags
$02 - TM0.2 TM0.1 TM0.0 R/W Timer0 Mode register (Prescaler)
$03
$04
$05
$06-$07
-
TL0.3
TH0.3
-
-
TL0.2
TH0.2
-
-
TL0.1
TH0.1
-
-
TL0.0
TH0.0
-
- Reserved
R/W Timer0 load/counter register low digit
R/W Timer0 load/counter register high digit
- Reserved
$08 PA.3 PA.2 PA.1 PA.0 R/W PORTA
$09 PB.3 PB.2 PB.1 PB.0 R/W PORTB
$0A PC.3 PC.2 PC.1 PC.0 R/W PORTC
$0B PD.3 PD.2 PD.1 PD.0 R/W PORTD
$0C PE.3 PE.2 PE.1 PE.0 R/W PORTE
$0D -
-
PF.1
PF.0 R/W PORTF
$0E TBR.3 TBR.2 TBR.1 TBR.0 R/W Table Branch Register
$0F INX.3 INX.2 INX.1 INX.0 R/W Pseudo index register
$10 DPL.3 DPL.2 DPL.1 DPL.0 R/W Data pointer for INX low nibble
$11 - DPM.2 DPM.1 DPM.0 R/W Data pointer for INX middle nibble
$12
$13 - $14
DPH.2
DPH.1
DPH.0
R/W Data pointer for INX high nibble
Reserved
Bit1:PBC interrupt rising / failing edge set
$15 PULLEN PH/PL PBCFR
- R/W Bit2:Port pull-hi/low set
Bit3: Port pull-up/low enable control
$16 PA3OUT PA2OUT PA1OUT PA0OUT R/W Set PORTA as an output port
$17 PB3OUT PB2OUT PB1OUT PB0OUT R/W Set PORTB as an output port
$18 PC3OUT PC2OUT PC1OUT PC0OUT R/W Set PORTC as an output port
$19 PD3OUT PD2OUT PD1OUT PD0OUT R/W Set PORTD as an output port
$1A PE3OUT PE2OUT PE1OUT PE0OUT R/W Set PORTE as an output port
$1B -
$1C -
$1D -
$1E WDT
- PF1OUT PF0OUT R/W Set PORTF as an output port
-
T0S
T0E
R/W
Bit0: T0 signal edge;
Bit1: T0 signal source
- - - - Reserved
- - - W Bit3: WDT timer reset (write 1 to reset WDT)
$1F - - - - - Reserved
* System Register $00 - $12 (except $07H) refer to "SH6610C User manual".
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6. T0 & WDT
System Register $1C
Address BIT3
$1C -
BIT2
-
BIT1
T0S
BIT0
T0E
T0E: T0 signal edge
0: Increment on low-to-high transition T0 pin (Power on initial)
1: Increment on high-to-low transition T0 pin
T0S: T0 signal source.
0: OSC 1/4 (Power on initial).
1: Transition on T0 pin.
T0
TOE
OSC/4
EOR
T0S
0
M
U
1X
Built-in RC
Oscillator
WDT Enable
(OTP option )
WDT reset
WDT & Warm
Up Counter
R/W Remark
W
Bit0: T0 signal edge
Bit1: T0 signal source
TIMER0 (8bits)
3
TM0 [2:0]
3
WDT Timeout
SH69P25
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH69P25.PDF ] | |
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