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PDF MAX3841 Data sheet ( Hoja de datos )
| Número de pieza | MAX3841 | |
| Descripción | CML 2 2 Crosspoint Switch | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-2905; Rev 0; 8/03
12.5Gbps CML 2 × 2 Crosspoint Switch
General Description
The MAX3841 is a low-power, 12.5Gbps 2 × 2 cross-
point switch IC for high-speed serial data loopback,
redundancy, and switching applications. The MAX3841
current-mode logic (CML) inputs and outputs have iso-
lated VCC connections to enable DC-coupled interfaces
to 1.8V, 2.5V, or 3.3V CML ICs. Fully differential signal
paths and Maxim’s second-generation SiGe technology
provide optimum signal integrity, minimizing jitter,
crosstalk, and signal skew. The MAX3841 is ideal for
serial OC-192 and 10GbE optical module, line card,
switch fabric, and similar applications.
The MAX3841 has 150mVP-P minimum differential input
sensitivity, and 500mVP-P nominal differential output
swing. Unused outputs can be powered down individu-
ally to conserve power. In addition to functioning as a 2
× 2 switch, the MAX3841 can be configured as a 2:1
multiplexer, 1:2 buffer, or dual 1:1 buffer. The MAX3841
is available in a 4mm × 4mm 24-pin thin QFN package,
and consumes only 215mW with both outputs enabled.
Applications
OC-192, 10GbE Switch/Line Cards
OC-192, 10GbE Optical Modules
System Redundancy/Self Test
Clock Fanout
Features
o Up to 12.5Gbps Operation
o Less Than 10psP-P Deterministic Jitter
o Less Than 0.7psRMS Random Jitter
o 1.8V, 2.5V, and 3.3V DC-Coupled CML I/O
o Independent Output Power-Down
o 4mm × 4mm Thin QFN Package
o -40°C to +85°C Operation
o +3.3V Core Supply
o 215mW Power Consumption (Excluding
Termination Currents)
Ordering Information
PART
TEMP RANGE
MAX3841ETG -40°C to +85°C
PIN-
PACKAGE
24 Thin QFN
PKG.
CODE
T2444-1
Pin Configuration appears at end of data sheet.
Typical Application Circuit
3.3V 2.5V
10Gbps
SERIAL
OPTICAL
MODULE
SDI+
SDI-
SDO+
SDO-
2.5V 3.3V 1.8V
VCC1OUT
OUT1+
VCC
VCC2IN
IN2+
OUT1-
IN1+
MAX3841
IN2-
OUT2+
IN1-
2.5V
OUT2-
1.8V
VCC1IN
VCC2OUT
SEL1 SEL2 ENO1 ENO2 GND
1.8V
10Gbps
CDR/SERDES
ASIC
SDO+
SDO-
SDI+
SDI-
LOOPBACK
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
12.5Gbps CML 2 × 2 Crosspoint Switch
V-
600mV
MAX
V+
(V+) - (V-)
1200mV
MAX
Figure 2. Definition of Differential Voltage Swing
VCC_IN
50Ω 50Ω
IN_+
IN_-
MAX3841
Figure 3. Equivalent CML Input Circuit
VCC_OUT
50Ω 50Ω
MAX3841
75mV
MIN
150mV
MIN
OUT_+
OUT_-
Table 1. Output Controls
ENO1
0
0
0
0
1
ENO2
0
0
0
0
1
SEL1
0
0
1
1
X
SEL2
0
1
0
1
X
OUT1
IN2
IN2
IN1
IN1
Disabled
OUT2
IN1
IN2
IN1
IN2
Disabled
Applications Information
Select and Enable Controls
The MAX3841 provides two LVCMOS-compatible
select inputs, SEL1 and SEL2. Either data input can be
connected to either or both data outputs. The MAX3841
provides two LVCMOS-compatible enable inputs,
ENO1 and ENO2, so each output can be disabled
independently. The MAX3841 can also be used as a
1:2 driver, 2:1 multiplexer, or a dual 1:1 buffer by using
the LVCMOS control inputs accordingly (see Table 1).
Power-Supply Connections
Each of the input and output power-supply connections
(VCC1IN, VCC2IN, VCC1OUT, VCC2OUT) is indepen-
dent and need not be connected to the same voltage.
The input and output supplies can be connected to
1.8V, 2.5V, or 3.3V, but the core supply (VCC) must be
connected to 3.3V for proper operation.
Input and Output Interfaces
The MAX3841 inputs and outputs can be AC-coupled
or DC-coupled according to the application. If an input
or output is not used it should be terminated with 50Ω
to the correct input or output supply voltage. For more
information about interfacing with logic families, refer to
Maxim application note HFAN-01.0: Introduction to
LVDS, PECL, and CML.
Package and Layout Considerations
The MAX3841 is packaged in a 4mm × 4mm 24-pin thin
QFN with exposed pad. The exposed pad provides
thermal and electrical connectivity to the IC and must
be soldered to a high-frequency ground plane. Use
multiple vias to connect the exposed pad underneath
the package to the PC board ground plane.
Use good layout techniques for the 10Gbps PC board
transmission lines, and configure the layout near the IC to
minimize impedance discontinuities. Power-supply
decoupling capacitors should be located as close as
possible to the IC.
Figure 4. Equivalent CML Output Circuit
_______________________________________________________________________________________ 5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAX3841.PDF ] | |
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