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Número de pieza | LP62S2048V-70LLT | |
Descripción | 256K X 8 BIT LOW VOLTAGE CMOS SRAM | |
Fabricantes | AMIC Technology | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de LP62S2048V-70LLT (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
No Preview Available ! LP62S2048-T Series
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Features
n Power supply range: 2.7V to 3.3V
n Access times: 70/100 ns (max.)
n Current:
Low power version:
Operating: 30mA (max.)
Standby: 50µA (max.)
Very low power version: Operating: 30mA (max.)
Standby: 10µA (max.)
n Full static operation, no clock or refreshing required
n All inputs and outputs are directly TTL-compatible
n Common I/O using three-state output
n Output enable and two chip enable inputs for easy
application
n Data retention voltage: 2V (min.)
n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)
and 36-pin CSP packages
General Description
The LP62S2048-T is a low operating current 2,097,152-
bit static random access memory organized as 262,144
words by 8 bits and operates on a low power supply
range: 2.7V to 3.3V. It is built using AMIC's high
performance CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable inputs are provided for POWER-DOWN
and device enable and an output enable input is included
for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2V.
Pin Configurations
n SOP
n TSOP/(TSSOP)
n CSP (Chip Size Package)
36-pin Top View
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE1
21 I/O8
20 I/O7
19 I/O6
18 I/O5
17 I/O4
16 1
17 32
123456
A A0 A1 CE2 A3 A6 A8
B I/O5 A2 WE A4 A7 I/O1
C I/O6
NC A5
I/O2
D GND
VCC
E VCC
GND
F I/O7
NC A17
I/O3
G I/O8 OE CE1 A16 A15 I/O4
H A9 A10 A11 A12 A13 A14
Pin No.
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Pin
Name
A11 A9 A8 A13 WE CE2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4
Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin
Name
A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE1 A10 OE
(August, 2001, Version 1.0)
1 AMIC Technology, Inc.
1 page LP62S2048-T Series
DC Electrical Characteristics (continued)
Symbol
ISB
Parameter
LP62S2048-70LT/10LT
Min.
Max.
LP62S2048-70LLT/10LLT
Min.
Max.
Unit
Conditions
- 0.5
-
0.5 mA CE1 = VIH or CE2 =VIL
ISB1 Standby Power
Supply Current
ISB2
Output Low
VOL Voltage
Output High
VOH Voltage
-
-
-
2.2
50
50
0.4
-
-
-
-
2.2
CE1 ≥ VCC - 0.2V
10 µA VIN ≥ 0V
10
µA
CE2 ≤ 0.2V
VIN ≥ 0V
0.4 V IOL = 2.1mA
- V IOH = -1.0mA
Truth Table
Mode
CE1 CE2
Standby
HX
XL
Output Disable
L
H
Read
LH
Write
LH
Note: X = H or L
OE
X
X
H
L
X
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
CIN* Input Capacitance
CI/O*
Input/Output Capacitance
* These parameters are sampled and not 100% tested.
WE
I/O Operation
Supply Current
X
High Z
ISB, ISB1
X
High Z
ISB, ISB2
H
High Z
ICC, ICC1, ICC2
H DOUT
ICC, ICC1, ICC2
L DIN
ICC, ICC1, ICC2
Max.
6
8
Unit
pF
pF
Conditions
VIN = 0V
VI/O = 0V
(August, 2001, Version 1.0)
5 AMIC Technology, Inc.
5 Page AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
LP62S2048-T Series
0.4V to 2.4V
5 ns
1.5V
See Figures 1 and 2
TTL TTL
CL
30pF
CL
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Data Retention Characteristics (TA = -25°C to 85°C)
Figure 2. Output Load for tCLZ1,
tCLZ2, tOHZ, tOLZ, tCHZ1,
tCHZ2, tWHZ, and tOW
Symbol
Parameter
Min.
Max.
Unit
Conditions
VDR1
VDR2
VCC for Data Retention
2.0 3.3 V CE1 ≥ VCC - 0.2V
2.0 3.3 V CE2 ≤ 0.2V,
ICCDR1
Data Retention Current
L-Version
LL-Version
-
-
20* VCC = 2.0V,
µA CE1 ≥ VCC - 0.2V,
5** VIN ≥ 0V
ICCDR2
L-Version
LL-Version
-
-
20* VCC = 2.0V,
µA CE2 ≤ 0.2V,
5** VIN ≥ 0V
tCDR Chip Disable to Data Retention Time
0
tR Operation Recovery Time
tRC
tVR VCC Rising Time from Data Retention Voltage 5
to Operating Voltage
- ns
- ns See Retention Waveform
- ms
** LP62S2048-70LLT/10LLT
* LP62S2048-70LT/10LT
ICCDR: max. 1µA at TA = 0°C to + 40°C
ICCDR: max. 5µA at TA = 0°C to + 40°C
(August, 2001, Version 1.0)
11 AMIC Technology, Inc.
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet LP62S2048V-70LLT.PDF ] |
Número de pieza | Descripción | Fabricantes |
LP62S2048V-70LLI | 256K X 8 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
LP62S2048V-70LLI | 256K X 8 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
LP62S2048V-70LLT | 256K X 8 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
LP62S2048V-70LLT | 256K X 8 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
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