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PDF HT46R71D-1 Data sheet ( Hoja de datos )
| Número de pieza | HT46R71D-1 | |
| Descripción | Dual Slope A/D Type MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT46R71D-1
Dual Slope A/D Type MCU with LCD
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
- HA0007E Using the MCU Look Up Table Instructions
- HA0049E Read and Write Control of the HT1380
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
· 10 bidirectional I/O lines and two ADC input
· One external interrupt input shard with an I/O lines
· One 8-bit and one 16-bit programmable timer/event
counter with overflow interrupt a 7-stage pre-scalar
· LCD driver with 10´3 segments
· 2K´14 program memory with partial lock function
· 32´8 data memory RAM
· Single differential input channel dual slope Analog to
Digital Converter with Operational Amplifier.
· Watchdog Timer with regulator power
· Buzzer output
· Internal 12kHz RC oscillator
· RC oscillator
· HALT function and wake-up feature reduce power
consumption
· Voltage regulator (3.3V) and charge pump
· Embeded voltage reference generator (1.5V)
· 4-level subroutine nesting
· Bit manipulation instruction
· 14-bit table read instruction
· Up to 1ms instruction cycle with 4MHz system clock
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
· Low voltage reset/detector function
· 48-pin SSOP package
General Description
The HT46R71D-1 is an 8-bit high performance, RISC
architecture microcontroller device specifically de-
signed for A/D with LCD applications that interface di-
rectly to analog signals, such as those from sensors.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, Dual slope A/D
converter, LCD display, HALT and wake-up functions,
watchdog timer, as well as low cost, enhance the versa-
tility of these devices to suit for a wide range of AD with
LCD application possibilities such as sensor signal pro-
cessing, scales, consumer products, subsystem con-
trollers, etc.
Rev. 1.00
1 May 14, 2007
1 page  
www.DataSheet4U.com
HT46R71D-1
Symbol
Parameter
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
ISTB4
Standby Current (WDT Disable 3V
No load, system HALT,
LCD on at HALT, 1/2 bias,
Internal RC 12kHz OSC ON)
5V VLCD=VDD
¾
¾
17
34
30
60
mA
mA
ISTB5
Standby Current (WDT Disable 3V
No load, system HALT
LCD on at HALT, 1/3 bias,
Internal RC 12kHz OSC ON)
5V VLCD=VDD
¾
¾
13
28
25
50
mA
mA
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0 ¾ 0.3VDD V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾ 0.7VDD ¾ VDD V
VIL2 Input Low Voltage (RES)
¾
¾
0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES)
¾
¾ 0.9VDD ¾ VDD V
VLCD LCD Highest Voltage
¾
¾
0 ¾ VDD V
VLVR Low Voltage Reset
¾¾
2 2.1 2.2
V
VLVD Low Voltage Detector
¾
¾
2.2 2.3
2.4
V
IOL1
I/O Port Segment Logic Output
Sink Current
3V
VOL=0.1VDD
5V
48
10 20
¾ mA
¾ mA
IOH1
I/O Port Segment Logic Output
Source Current
3V
VOH=0.9VDD
5V
-2 -4
¾ mA
-5 -10 ¾ mA
IOL2
LCD Common and Segment
Current
3V
VOL=0.1VDD
5V
210 420
350 700
¾
¾
mA
mA
IOH2
LCD Common and Segment
Current
3V
VOH=0.9VDD
5V
-80
-180
-160
-360
¾
¾
mA
mA
RPH
Pull-high Resistance of I/O Ports 3V
and INT
5V
¾
¾
20 60 100 kW
10 30 50 kW
Charge Pump and Regulator
VCHPI Input Voltage
Charge pump on
¾
Charge pump off
2.2 ¾ 3.6 V
3.7 ¾ 5.5 V
VREGO Output Voltage
¾ No load
3 3.3 3.6
V
VREGDP1
Regulator Output Voltage Drop
(Compare with No Load)
VREGDP2
VDD=3.7V~5.5V
¾ Charge pump off
Current£10mA
VDD=2.4V~3.6V
¾ Charge pump on
Current£6mA
¾ 100 ¾ mV
¾ 100 ¾ mV
Dual Slope AD, Amplifier and Band Gap
VRFGO Reference Generator Output
¾ @3.3V
1.45 1.5 1.55
V
VRFGTC
Reference Generator
Temperature Coefficient
¾ @3.3V
¾ 50
¾ Ppm/C
VICMR Common Mode Input Range
VADOFF Input Offset Range
¾ Amplifier, no load
¾ Integrator, no load
¾¾
0.2 ¾ VDD-1 V
1 ¾ VDD-0.2 V
¾ 500 800
mV
Rev. 1.00
5 May 14, 2007
5 Page 
www.DataSheet4U.com
HT46R71D-1
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
All interrupts will provide a wake-up function. As an in-
terrupt is serviced, a control transfer occurs by pushing
the contents of the program counter onto the stack fol-
lowed by a branch to a subroutine at the specified loca-
tion in the Program Memory. Only the contents of the
program counter is pushed onto the stack. If the con-
tents of the register or of the status register is altered by
the interrupt service program which corrupts the desired
control sequence, the contents should be saved in ad-
vance.
An external interrupt is triggered by an edge transition
on INT (A configuration option selects: high to low, low to
high, both low to high and high to low), and the related
interrupt request flag (EIF; bit 4 of INTC0) is set as well.
After the interrupt is enabled, the stack is not full, and
the external interrupt is active, a subroutine call to loca-
tion 04H occurs. The interrupt request flag (EIF) and
EMI bits are all cleared to disable other maskable inter-
rupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of INTC0), which is normally
caused by a timer overflow. After the interrupt is en-
abled, and the stack is not full, and the T0F bit is set, a
subroutine call to location 08H occurs. The related inter-
rupt request flag (T0F) is reset, and the EMI bit is
cleared to disable other maskable interrupts.
Timer/Event Counter 1 is operated in the same manner
but its related interrupt request flag is T1F (bit 6 of
INTC0) and its subroutine call location is 0CH.
The A/D Converter interrupt is initialized by setting the
A/D Converter clock interrupt request flag (ADF; bit 4 of
INTC1), that is caused by an A/D conversion done sig-
nal. After the interrupt is enabled, and the stack is not
full, and the ADF bit is set, a subroutine call to location
10H occurs. The related interrupt request flag (ADF) is
reset and the EMI bit is cleared to disable further
maskable interrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the ²RETI² instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, ²RET²
or ²RETI² may be invoked. RETI sets the EMI bit and en-
ables an interrupt service, but RET does not.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Interrupt Source
Priority Vector
External interrupt
1 04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
ADC interrupt
4 10H
Once the interrupt request flags (ADF, T0F, T1F, EIF)
are all set, they remain in the INTC1 or INTC0 respec-
tively until the interrupts are serviced or cleared by a
software instruction.
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. It¢s be-
cause interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applica-
tions. During that period, if only one stack is left, and en-
abling the interrupt is not well controlled, operation of
the ²call² in the interrupt subroutine may damage the
original control sequence.
Oscillator Configuration
The device provides two oscillator circuits, an external
RC oscillator and an internal RC 12kHz oscillator
(Int.RCOSC). The external RC oscillator signal is used
for the system clock while the Internal 12kHz RC oscilla-
tor is designated for timing purposes.
In the IDLE mode, the system oscillator will stop run-
ning, but if bit IRCC = 1,to enable the IRC clock source,
the internal RC oscillator (Int.RCOSC) will continue to
free run. In the HALT mode, if the IRC clock source is
disabled, with bit IRCC=0, both the system oscillator
and the internal RC oscillator will stop running. How-
ever, if the WDT is enabled, the internal RC oscillator will
continuously free run. The system can be woken-up
from either the IDLE or HALT mode by the occurrence of
an interrupt, a high to low transition on any of the Port A
pins, a WDT overflow or a timer overflow and request
flag is set (0®1). If an external RC oscillator is used, an
V DD
470pF
O SC1
N M O S O p e n D r a in
O SC2
R C O s c illa to r
System Oscillator
Rev. 1.00
11 May 14, 2007
11 Page | ||
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