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PDF DS91C176 Data sheet ( Hoja de datos )
| Número de pieza | DS91C176 | |
| Descripción | (DS91C176 / DS91D176) Multipoint-LVDS (M-LVDS) Transceivers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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February 2007
DS91D176/DS91C176
Multipoint-LVDS (M-LVDS) Transceivers
General Description
The DS91C176 and DS91D176 are high-speed M-LVDS dif-
ferential transceivers designed for multipoint applications with
multiple drivers or receivers. Multipoint LVDS (M-LVDS) is a
new bus interface standard (TIA/EIA-899) based on LVDS but
including several enhancements to improve multipoint per-
formance. M-LVDS devices have superior drive capability
and can support up to 32 loads. Along with increased drive,
M-LVDS devices are required to have a controlled edge rate
to minimize reflections and EMI. The 1 nSec minimum edge
rate is tolerant of stub lengths up to 2 inches in length. M-
LVDS devices also have a very large common mode range
for additional noise margin in heavily loaded and noisy back-
plane environments.
The DS91C176/DS91D176 are half-duplex transceivers that
accept LVTTL/LVCMOS signals at the driver inputs and con-
vert them to differential M-LVDS signal levels. The receiver
inputs accept low voltage differential signals (LVDS, B-LVDS,
M-LVDS, LV-PECL) and convert them to 3V LVCMOS sig-
nals. The DS91D176 has a M-LVDS type 1 receiver input with
no offset. The DS91C176 receiver contains an M-LVDS type
2 failsafe circuit with an internal 100 mV offset that provides
a LOW output for both short and open input conditions.
Features
■ Meets TIA/EIA-899 M-LVDS Standard
■ Capable of driving 32 LVDS loads
■ Controlled Edge Rates Tolerant to Stubs
■ Wide Common Mode for Increased Noise Immunity
■ DS91D176 has type 1 receiver input
■ DS91C176 has type 2 receiver with fail-safe
■ Up to 200 Mbps operation
■ Industrial temperature range
■ Single 3.3V supply
■ 8-lead SOIC package
Typical Application in AdvancedTCA Clock Distribution
© 2007 National Semiconductor Corporation 200246
20024630
www.national.com
1 page  
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 3, 8)
Symbol
Parameter
Conditions
Min Typ Max Units
DRIVER AC SPECIFICATION
tPLH Differential Propagation Delay Low to High
tPHL Differential Propagation Delay High to Low
tSKD1 (tsk(p))
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
tSKD3
Part-to-Part Skew (Notes 6, 9)
tTLH (tr)
Rise Time (Note 9)
tTHL (tf)
Fall Time (Note 9)
tPZH Enable Time (Z to Active High)
tPZL Enable Time (Z to Active Low )
tPLZ Disable Time (Active Low to Z)
tPHZ Disable Time (Active High to Z)
tJIT Random Jitter, RJ (Note 9)
fMAX Maximum Data Rate
RECEIVER AC SPECIFICATION
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
Figure 7 and Figure 8
RL = 50Ω, CL = 5 pF,
CD = 0.5 pF
Figure 9 and Figure 10
100 MHz Clock Pattern (Note 7)
1.3 3.4 5.0 ns
1.3 3.1 5.0 ns
300 420 ps
1.3 ns
1.0 1.8 3.0 ns
1.0 1.8 3.0 ns
8 ns
8 ns
8 ns
8 ns
2.5 5.5 psrms
200 Mbps
tPLH
tPHL
tSKD1 (tsk(p))
tSKD3
tTLH (tr)
tTHL (tf)
tPZH
tPZL
tPLZ
tPHZ
fMAX
Propagation Delay Low to High
Propagation Delay High to Low
Pulse Skew |tPLHD − tPHLD| (Notes 5, 9)
Part-to-Part Skew (Notes 6, 9)
Rise Time (Note 9)
Fall Time (Note 9)
Enable Time (Z to Active High)
Enable Time (Z to Active Low)
Disable Time (Active Low to Z)
Disable Time (Active High to Z)
Maximum Data Rate
CL = 15 pF
Figures 11, 12 and Figure 13
RL = 500Ω, CL = 15 pF
Figure 14 and Figure 15
2.0 4.7 7.5 ns
2.0 5.3 7.5 ns
0.6 1.7 ns
1.3 ns
0.5 1.2 2.5 ns
0.5 1.2 2.5 ns
10 ns
10 ns
10 ns
10 ns
200 Mbps
Note 1: “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
Note 3: All typicals are given for VCC = 3.3V and TA = 25°C.
Note 4: The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
Note 5: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 6: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
Note 7: Stimulus and fixture Jitter has been subtracted.
Note 8: CL includes fixture capacitance and CD includes probe capacitance.
Note 9: Not production tested. Guaranteed by a statistical analysis on a sample basis at the time of characterization.
5 www.national.com
5 Page 
Function Tables
DS91D176/DS91C176 Transmitting
Inputs
RE DE
D
X 2.0V 2.0V
X 2.0V 0.8V
X 0.8V X
Outputs
BA
LH
HL
ZZ
X — Don't care condition
Z — High impedance state
RE
0.8V
0.8V
0.8V
2.0V
DS91D176 Receiving
Inputs
Output
DE A − B
R
0.8V
0.8V
0.8V
≥ +0.05V
≤ −0.05V
0V
H
L
X
0.8V
X
Z
X — Don't care condition
Z — High impedance state
RE
0.8V
0.8V
0.8V
2.0V
DS91C176 Receiving
Inputs
Output
DE A − B
R
0.8V
0.8V
0.8V
≥ +0.15V
≤ +0.05V
0V
H
L
L
0.8V
X
Z
X — Don't care condition
Z — High impedance state
DS91D176 Receiver Input Threshold Test Voltages
Applied Voltages
VIA
2.400V
0.000V
3.800V
3.750V
−1.400V
−1.350V
VIB
0.000V
2.400V
3.750V
3.800V
−1.350V
−1.400V
Resulting Differential Input
Voltage
VID
2.400V
−2.400V
0.050V
−0.050V
−0.050V
0.050V
Resulting Common-Mode
Input Voltage
VIC
1.200V
1.200V
3.775V
3.775V
−1.375V
−1.375V
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
Receiver
Output
R
H
L
H
L
H
L
DS91C176 Receiver Input Threshold Test Voltages
Applied Voltages
VIA
2.400V
0.000V
3.800V
3.800V
−1.250V
−1.350V
VIB
0.000V
2.400V
3.650V
3.750V
−1.400V
−1.400V
Resulting Differential Input
Voltage
VID
2.400V
−2.400V
0.150V
0.050V
0.150V
0.050V
Resulting Common-Mode
Input Voltage
VIC
1.200V
1.200V
3.725V
3.775V
−1.325V
−1.375V
H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
Receiver
Output
R
H
L
H
L
H
L
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS91C176.PDF ] | |
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