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PDF SY89544U Data sheet ( Hoja de datos )
| Número de pieza | SY89544U | |
| Descripción | DIFFERENTIAL 4:1 LVDS MULTIPLEXER | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Micrel, Inc.
2.5V, 3.2Gbps, DIFFERENTIAL 4:1
LVDS MULTIPLEXER WITH
INTERNAL INPUT TERMINATION
Precision Edge®
Precision ESdY8g9e5®44U
SY89544U
FEATURES
Selects among four differential inputs
Guaranteed AC performance over temp and voltage:
Precision Edge®
• DC-to > 3.2Gbps data rate throughput
DESCRIPTION
• < 600ps In-to-Out tpd
• < 150ps tr/tf
Ultra low-jitter design:
• < 1psRMS random jitter
• < 10psPP deterministic jitter
• < 10psPP total jitter (clock)
• < 0.7psRMS crosstalk-induced jitter
Unique input isolation design minimizes crosstalk
Internal input termination
The SY89544U is a fast, low-jitter, 4:1 differential MUX
with an LVDS (350mV) compatible output with guaranteed
data rate throughput of 3.2Gbps over temperature and
voltage.
The SY89544U differential inputs include a unique, 3-pin
internal termination that allows access to the termination
network through a VT pin. This feature allows the device to
easily interface to different logic standards, both AC- and
DC-coupled without external resistor-bias and termination
Unique input termination and VT pin accepts DC-
Coupled and AC-Coupled inputs (LVDS, LVPECL,
networks. The result is a clean, stub-free, low-jitter interface
solution.
CML)
The SY89544U operates from a single 2.5V supply and
350mV LVDS output swing
is guaranteed over the full industrial temperature range
CMOS/TTL compatible MUX select
(–40°C to +85°C). For applications that require a 3.3V supply,
Power supply 2.5V ±5%
consider the SY89545L. For applications that require two
–40°C to +85°C temperature range
differential outputs, consider the SY89546U or SY89547L.
The SY89544U is part of Micrel’s Precision Edge® product
Available in 32-pin (5mm × 5mm) MLF® package family.www.DataSheet4U.com
APPLICATIONS
All support documentation can be found on Micrel’s web
site at www.micrel.com.
SONET/SDH channel select applications
FUNCTIONAL BLOCK DIAGRAM
Fibre Channel multi-channel select applications
Gigabit Ethernet multi-channel select
TYPICAL PERFORMANCE
Output Amplitude
vs. Frequency
400
350
300
250
200
150
IN0
50Ω
VT0
50Ω
/IN0
IN1
50Ω
VT1
50Ω
/IN1
IN2
50Ω
VT2
50Ω
/IN2
4:1 MUX
0
1
MUX
2
S1
3 S0
LVDS
Q
/Q
100
50
00
12345
FREQUENCY (GHz)
6
IN3
50Ω
VT3
50Ω
/IN3
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-020707
[email protected] or (408) 955-1690
1
SEL0
SEL1
Rev.: C Amendment: /0
Issue Date: February 2007
1 page  
Micrel, Inc.
Precision Edge®
SY89544U
AC ELECTRICAL CHARACTERISTICS(10)
VCC = 2.5V ±5%; TA = –40°C to +85°C; RL = 100Ω across Q and /Q, unless otherwise stated.
Symbol
Parameter
Condition
fMAX
tpd
Maximum Operating Frequency
Differential Propagation Delay
VOUT ≥ 200mV
IN-to-Q
SEL-to-Q
NRZ Data
Clock
tSKEW
Input-to-Input Skew
Part-to-Part Skew
Note 11
Note 12
tJITTER
Data
Random Jitter (RJ) Note 13
Deterministic Jitter (DJ) Note 14
Clock
Total Jitter (TJ) Note 15
Cycle-to-Cycle Jitter Note 16
Crosstalk-Induced Jitter
Note 17
Adjacent Channel
tr, tf Output Rise/Fall Time
(20% to 80%)
At full output swing.
Min Typ Max Units
3.2 Gbps
4 GHz
310 410 510
ps
200 400 700
ps
5 20 ps
200 ps
1 psRMS
10 psPP
10 psPP
1 psRMS
0.7 psRMS
35 80 150 ps
Notes:
10. Measured with 100mV input swing. See “Timing Diagrams” section for definition of parameters. High-frequency AC parameters are guaranteed by
design and characterization.
11. Input-to-input skew is the difference in propagation delay between any two inputs to the output under identical conditions.
12. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
13. Random jitter is measured with a K28.7 comma detect character pattern, measured at 1.25Gbps and 3.2Gbps.
14. Deterministic jitter is measured at 1.25Gbps and 3.2Gbps, with both K28.5 and 223–1 PRBS pattern.
15. Total jitter definition: with an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will deviate by more than the
specified peak-to-peak jitter value.
16. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn-1 where T is the time between rising edges of the output
signal.
17. Crosstalk is measured at the output while applying two similar frequencies to adjacent inputs that are asynchronous with respect to each other at the
inputs.
M9999-020707
[email protected] or (408) 955-1690
5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SY89544U.PDF ] | |
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