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PDF SY89464U Data sheet ( Hoja de datos )

Número de pieza SY89464U
Descripción Precision LVPECL 1:10 Fanout
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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No Preview Available ! SY89464U Hoja de datos, Descripción, Manual

SY89464U
Precision LVPECL 1:10 Fanout with 2:1 Runt
Pulse Eliminator MUX and Internal Termination
General Description
The SY89464U is a low jitter 1:10 LVPECL fanout
buffer with a 2:1 differential input multiplexer (MUX)
optimized for redundant source switchover
applications. Unlike standard multiplexers, the
SY89464U’s unique 2:1 Runt Pulse Eliminator
(RPE) MUX prevents any short cycles or “runt”
pulses during switchover. In addition, a unique Fail-
Safe Input (FSI) protection prevents metastable
output conditions when the selected input clock fails
Features
Precision Edge®
Selects between two sources, and provides 10
precision LVPECL copies
Guaranteed AC performance over temperature and
supply voltage:
to a DC voltage (voltage between the pins of the
– Wide operating frequency: 1kHz to >1.5GHz
differential input drops below 100mV).
– < 1100ps In-to-Out tpd
The differential input includes Micrel’s unique, 3-pin
– < 220ps tr/tf
internal termination architecture that allows Unique, patent-pending MUX input isolation design
customers to interface to any differential signal (AC-
minimizes adjacent channel crosstalk
own1gT±iSEAwnue01rhdlYeidltat00egbhu8wsDrK%eos9ausoS®Ct-u4npirrctYik6tp-etpaoesc8s4rolmaeuaoo9Urtitdpdnunte4p:upymp6daiwttsocllh4otypewtileUbcbpeedlwiuelavrn)asea.moreeimnltgtepla.uLednisoescrnVsasferrtahPleiatMssrthilpEtef.amicatiaoCcsniognntanrghLmuegfl2e.rlcalo.’2Twasrooam0ahnifrsphtneh–siabtgt4.oe1eehf02ue0ar-mf°.tds0so5pCptmiuVunenottrVasoei±dvstdi5aee+oo,(%rr/82nefnPa50trl°8roM0hleCe0rmecist0.cii3imVsrmsT.efi3PtoheuVlowP’Vnesswl)r,lw.DataSh••••••eet4UFU––––UaL82O.ccV0.aolnu<<<<5mtc0irDitlV1110qae-pmSSpp0.u-pu7±lVsspa)eottp5sRRsfwes%eLpMMPDnRVaPSSjIMaiCntotPtrceStboapr-eyEnltMnuec3raatCdtel.nldUe3Lopdjde-iXVtmrtsotioeAneic±u-gvCtrjcri1teentop(y-t0rn:cecsucn%tlosrltosaetuclaospjktliusektl)tecpreimdinprlldlaiiynnutiapvoctuoeniotldstsnaj(giaCtetneMdrLV, TPEpiCnL,
-40°C to +85°C industrial temperature range
Available in 44-pin (7mm x 7mm) MLF™ package
Applications
Redundant clock switchover
Fail-safe clock protection
Markets
LAN/WAN
Enterprise servers
ATE
Test and measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
December 2005
M9999-120105-B
[email protected] or (408) 955-1690

1 page




SY89464U pdf
Micrel, Inc.
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................ –0.5V to +4.0V
Input Voltage (VIN) ....................................–0.5V to VCC
LVPECL Output Current (IOUT) ......................................
Continuous .................................................... 50mA
Surge ........................................................... 100mA
Input Current (IIN) ...........................................................
IN, /IN........................................................... ±50mA
VT ............................................................... ±100mA
VREF-AC Current
Source/Sink Current on VREF-AC.................... ±2mA
Lead Temperature (soldering, 20 sec.)............ +260°C
Storage Temperature (Ts) ...................–65°C to 150°C
SY89464U
Operating Ratings(2)
Supply Voltage (VCC) ....................+2.375V to +2.625V
........................................................ +3.0V to +3.6V
APmacbkiaegnet TTehmerpmeraal tRureesi(sTtaA)n.c..e..(.3.)........... –40°C to +85°C
MLF™ (θ JA)
Still-Air ..................................................... 24.4°C/W
MLF™ (ψ JB)
Junction-to-Board ..................................... 8.1°C/W
DC Electrical Characteristics(4)
TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max Units
VCC Power Supply
2.375 2.5 2.625 V
3.0 3.3 3.6 V
ICC
RIN
RDIFF_IN
Power Supply Current
Input Resistance
(IN-to-VT)
Differential Input Resistance
(IN-to-/IN)
No load, max VCC
120 160 mA
45 50 55
90 100 110
VIH Input High Voltage
(IN, /IN)
1.2
VCC
V
VIL Input Low Voltage
(IN, /IN)
0
VIH–0.1
V
VIN Input Voltage Swing
(IN, /IN)
See Figure 1a. Note 5.
0.1
2.5 V
VDIFF_IN
Differential Input Voltage Swing
|IN-/IN|
See Figure 1b.
0.2
V
VIN_FSI
Input Voltage Threshold that
Triggers FSI
30 100 mV
VT_IN
IN-to-VT
(IN, /IN)
1.28 V
VREF-AC Output Reference Voltage
VCC–1.3 VCC–1.2 VCC–1.1
V
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and
ψJB values are determined for a 4-layer board in still air unless otherwise stated.
4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
5. VIN (max) is specified when VT is floating.
December 2005
5 M9999-120105-B
[email protected] or (408) 955-1690

5 Page





SY89464U arduino
Micrel, Inc.
Case #4: Input Clock Failure: Switching from the
selected clock input stuck in an undetermined state
to a valid clock input (RPE-enabled).
If CLK1 fails to an undetermined state (e.g.,
amplitude falls below the 100mV (VIN) minimum
single-ended input limit, or 200mV differentially)
before the RPE MUX selects CLK2 (using the SEL
pin), the switchover to the valid clock CLK2 will
occur either following Case #2 or Case #3,
depending upon the last valid state at the CLK1.
SY89464U
If the selected input clock fails to a floating, static, or
extremely low signal swing, including 0mV, the FSI
function will eliminate any metastable condition and
guarantee a stable output signal. No ringing and no
undetermined state will occur at the output under
these conditions.
Please note that the FSI function will not prevent
duty cycle distortions or runt pulses in case of a
slowly deteriorating (but still toggling) input signal.
Due to the FSI function, the propagation delay will
depend upon rise and fall time of the input signal
and on its amplitude. Refer to “Typical Operating
Characteristics” for detailed information.
Timing Diagram 4
December 2005
11 M9999-120105-B
[email protected] or (408) 955-1690

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