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PDF LT1189 Data sheet ( Hoja de datos )

Número de pieza LT1189
Descripción Low Power Video Difference Amplifier
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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LT1189
Low Power
Video Difference Amplifier
FEATURES
s Differential or Single-Ended Gain Block (Adjustable)
s –3dB Bandwidth, AV = ± 10
s Slew Rate
35MHz
220V/µs
s Low Supply Current
13mA
s Output Current
± 20mA
s CMRR at 10MHz
48dB
s LT1193 Pin Out
s Low Cost
s Single 5V Operation
s Drives Cables Directly
s Output Shutdown
APPLICATI S
s Line Receivers
s Video Signal Processing
s Cable Drivers
s Tape and Disc Drive Systems
DESCRIPTIO
The LT1189 is a difference amplifier optimized for opera-
tion on ±5V, or a single 5V supply, and gain 10. This
versatile amplifier features uncommitted high input im-
pedance (+) and (–) inputs, and can be used in differential
or single-ended configurations. Additionally, a second set
of inputs give gain adjustment and DC control to the
difference amplifier.
The LT1189’s high slew rate, 220V/µs, wide bandwidth,
35MHz, and ±20mA output current require only 13mA of
supply current. The shutdown feature reduces the power
dissipation to a mere 15mW, and allows multiple amplifi-
ers to drive the same cable.
The LT1189 is a low power, gain of 10 stable version of the
popular LT1193, and is available in 8-pin miniDIPs and SO
packages. For lower gain applications see the LT1187
data sheet.
TYPICAL APPLICATI
Cable Sense Amplifier for Loop Through Connections
with DC Adjust
VIN
CABLE
VDC
5V
3
+
2
7
1
LT1189
+
8– 4
–5V
909
6
VOUT
100
LT1189 • TA01
Closed-Loop Gain vs Frequency
50
40
30
20
10
0
0.1
VS = ±5V
RL = 1k
1 10
FREQUENCY (MHz)
100
LT1189 • TA02
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LT1189 pdf
TYPICAL PERFOR A CE CHARACTERISTICS
Input Bias Current vs
Common-Mode Voltage
3.0
VS = ±5V
2.5
2.0
1.5
–55°C
1.0
0.5 25°C
0 125°C
– 0.5
–5 –4 –3 –2 –1 0 1 2 3 4 5
COMMON-MODE VOLTAGE (V)
LT1189 • TPC01
Equivalent Input Noise Voltage vs
Frequency
200
180
VS = ±5V
TA = 25°C
160 RS = 0
140
120
100
80
60
40
20
0
10 100 1k 10k 100k
FREQUENCY (Hz)
LT1189 • TPC04
Shutdown Supply Current vs
Temperature
6.0
VS = ±5V
5.0
4.0 VS/D = –VEE + 0.6V
VS/D = –VEE + 0.4V
3.0
2.0 VS/D = –VEE + 0.2V
1.0
0
–50 –25
VS/D = –VEE
0 25 50 75 100 125
TEMPERATURE (°C)
LT1189 • TPC07
Input Bias Current vs Temperature
100
VS = ±5V
0
+IB
–100
–IB
– 200
IOS
– 300
– 400
–50 –25
0 25 50 75 100 125
TEMPERATURE (°C)
LT1189 • TPC02
Equivalent Input Noise Current vs
Frequency
12
VS = ±5V
10
TA = 25°C
RS = 100k
8
6
4
2
0
10 100 1k 10k 100k
FREQUENCY (Hz)
LT1189 • TPC05
Gain Error vs Temperature
–1.2
VS = ±5V
–1.4
VOUT = ±1V
AV = 10
RL = 1k
–1.6
–1.8
–2.0
–2.2
–2.4
–50 –25
0 25 50 75 100 125
TEMPERATURE (°C)
LT1189 • TPC08
LT1189
Common-Mode Voltage vs
Temperature
V+
–0.5 V+ = 1.8V TO 9V
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
V
– 50 –25
V+ = –1.8V TO –9V
0 25 50 75 100 125
TEMPERATURE (°C)
LT1189 • TPC03
Supply Current vs Supply Voltage
16
– 55°C
14
25°C
12
125°C
10
8
0 2 4 6 8 10
±SUPPLY VOLTAGE (V)
LT1189 • TPC06
Open-Loop Gain vs Temperature
16
14
VS = ±5V
VO = ±3V
RL = 1k
12
10
RL = 500
8
6
4
2
0
–50 –25
0 25 50 75 100 125
TEMPERATURE (°C)
LT1189 • TPC09
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LT1189 arduino
APPLICATI S I FOR ATIO
1MHz Sine Wave Gated Off with Shutdown Pin
SHUTDOWN
VOUT
LT1189
The ability to maintain shutoff is shown on the curve Shut
down Supply Current vs Temperature in the Typical Per-
formance Characteristics section. At very high elevated
temperature it is important to hold the shutdown pin close
to the negative supply to keep the supply current from
increasing.
AV = 10, RFB = 900, RG = 100
LT1189 • AI10
TYPICAL APPLICATI
Differential Receiver MUX for Power Down Applications
15k
CABLE 1
15k
1.5k
CMOS IN
CHANNEL SELECT
1.5k
3 + 5V
27
VDC
1
8
LT1189
REF 4
FB 5
1k –5V
6
1k 100
74HC04
74HC04
CABLE 2
1k
15k
– 5V
1.5k
15k
1.5k
5V
VDC
3
2
+
5
7
1
8
LT1189
REF 4
6
FB
–5V
100
1k
VOUT
1% RESISTORS WORST CASE CMRR = 28dB
TYPICALLY 35dB
LT1189 • TA03
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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