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PDF MC74HC174A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC174A | |
| Descripción | Hex D Flip-Flop | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MC74HC174A
Hex D Flip−Flop with
Common Clock and Reset
High−Performance Silicon−Gate CMOS
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active−low.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 162 FETs or 40.5 Equivalent Gates
• Pb−Free Packages are Available*
16
1
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MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC174AN
AWLYYWWG
1
16
1
16
1
16
SOIC−16
D SUFFIX
CASE 751B
HC174AG
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HC
174A
ALYWG
G
1
16
1
SOEIAJ−16
F SUFFIX
CASE 966
16
74HC174A
ALYWG
1
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 10
1
Publication Order Number:
MC74HC174A/D
1 page  
MC74HC174A
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC *55_C to 25_C
v85_C
v125_C
Symbol
Parameter
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtsu Minimum Setup Time, Data to Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎth MinimumHoldTime,ClocktoData
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtrec MinimumRecoveryTime,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎReset Inactive to Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw Minimum Pulse Width, Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtw MinimumPulseWidth,Reset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr,tf MaximumInputRiseandFallTimes
Figure
6
6
5
4
5
4
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Min Max Min Max Min Max Unit
50 65 75 ns
10 13 15
9.0 11 13
5.0 5.0 5.0 ns
5.0 5.0 5.0
5.0 5.0 5.0
5.0 5.0 5.0 ns
5.0 5.0 5.0
5.0 5.0 5.0
75 95 110 ns
15 19 22
13 16 19
75 95 110 ns
15 19 22
13 16 19
1000
500
400
1000
500
400
1000
500
400
ns
CLOCK
D0
RESET
9
3
1
D1 4
D2 6
D3 11
D4 13
D5 14
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
C
Q
DR
2 Q0
5 Q1
7 Q2
10 Q3
12 Q4
15 Q5
Figure 3. Expanded Logic Diagram
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC74HC174A.PDF ] | |
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