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PDF SST39W800A Data sheet ( Hoja de datos )
| Número de pieza | SST39W800A | |
| Descripción | 8 Mbit (x16) Multi-Purpose Flash | |
| Fabricantes | SST | |
| Logotipo |  |
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8 Mbit (x16) Multi-Purpose Flash
SST39WF800A
FEATURES:
SST39WF800A1.8V 8Mb (x16) MPF memory
Data Sheet
• Organized as 512K x16
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 5 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 90 ns
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (5mm x 6mm) Micro-Package
– 48-ball XFLGA (5mm x 6mm) Micro-Package
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST39WF800A device is a 512K x16 CMOS Multi-
Purpose Flash (MPF) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39WF800A writes (Pro-
gram or Erase) with a 1.65-1.95V power supply. This
device conforms to JEDEC standard pin assignments for
x16 memories.
Featuring high-performance Word-Program, the
SST39WF800A device provides a typical Word-Program
time of 28 µsec. The device uses Toggle Bit or Data# Poll-
ing to detect the completion of the Program or Erase opera-
tion. To protect against inadvertent writes, it has on-chip
hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, this device is offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at
greater than 100 years.
The SST39WF800A device is suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
it significantly improves performance and reliability, while
lowering power consumption. It inherently uses less energy
©2006 Silicon Storage Technology, Inc.
S71258-05-000
7/06
1
during Erase and Program than alternative flash technolo-
gies. When programming a flash device, the total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility
while lowering the cost for program, data, and configuration
storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet surface mount requirements, the SST39WF800A
is offered in a 48-ball TFBGA package and a 48-ball Micro-
Package. See Figure 3 and Figure 2 for pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
8 Mbit Multi-Purpose Flash
SST39WF800A
Data Sheet
X-Decoder
Memory Address
Address Buffer & Latches
CE#
OE#
WE#
Control Logic
FIGURE 1: Functional Block Diagram
SuperFlash
Memory
Y-Decoder
I/O Buffers and Data Latches
DQ15 - DQ0
1258 B1.0
TOP VIEW (balls facing down)
SST39WF800A
6
A2 A4 A6 A17 NC NC WE# NC A9 A11
5
A1 A3 A7 NC
NC A10 A13 A14
4
A0 A5 A18
3
A8 A12 A15
CE# DQ8 DQ10
2
DQ4 DQ11 A16
VSS OE# DQ9 NC
1
NC DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS
AB C D E F G H J K L
FIGURE 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA
©2006 Silicon Storage Technology, Inc.
5
S71258-05-000
7/06
5 Page 
8 Mbit Multi-Purpose Flash
SST39WF800A
AC CHARACTERISTICS
Data Sheet
TABLE 12: Read Cycle Timing Parameters
Symbol Parameter
Min Max Units
TRC Read Cycle Time
90 ns
TCE Chip Enable Access Time
90 ns
TAA Address Access Time
90 ns
TOE
TCLZ1
TOLZ1
TCHZ1
TOHZ1
TOH1
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
50 ns
0 ns
0 ns
40 ns
40 ns
0 ns
T12.0 1258
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: Program/Erase Cycle Timing Parameters
Symbol Parameter
Min Max Units
TBP Word-Program Time
40 µs
TAS Address Setup Time
0 ns
TAH Address Hold Time
50 ns
TCS WE# and CE# Setup Time
0 ns
TCH WE# and CE# Hold Time
0 ns
TOES
OE# High Setup Time
0 ns
TOEH
OE# High Hold Time
10 ns
TCP CE# Pulse Width
50 ns
TWP
TWPH1
TCPH1
WE# Pulse Width
WE# Pulse Width High
CE# Pulse Width High
50 ns
30 ns
30 ns
TDS
TDH1
TIDA1
Data Setup Time
Data Hold Time
Software ID Access and Exit Time
50 ns
0 ns
150 ns
TSE Sector-Erase
50 ms
TBE Block-Erase
50 ms
TSCE
Chip-Erase
200 ms
T13.0 1258
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
11
S71258-05-000
7/06
11 Page | ||
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