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PDF MX26C2000B Data sheet ( Hoja de datos )
| Número de pieza | MX26C2000B | |
| Descripción | CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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ADVANCE INFORMATION
MX26C2000B
FEATURES
• 256Kx 8 organization
• Single +5V power supply
• +12V programming voltage
• Fast access time:90/100/120/150 ns
• Totally static operation
• Completely TTL compatible
• Operating current:30mA
• Standby current: 100uA
GENERAL DESCRIPTION
The MX26C2000B is a 5V only, 2M-bit, MTP EPROMTM
(Multiple Time Programmable Read Only Memory). It is
organized as 256K words by 8 bits per word, operates
from a single + 5 volt supply, has a static standby mode,
and features fast single address location programming.
All programming signals are TTL levels, requiring a single
pulse. It is design to be programmed and erased by an
2M-BIT [256K x 8] CMOS
MULTIPLE-TIME-PROGRAMMABLE-EPROM
• Chip erase time: 1 (typ.)
• Chip program time: 12.5 (typ.)
• 50 minimum erase/program cycles
• Typical fast programming cycle duration 10us/byte
• Package type:
- 32 pin plastic DIP
- 32 pin PLCC
- 32 pin TSOP
- 32 pin SOP
EPROM programmer or on-board. The MX26C2000B
supports a intelligent fast programming algorithm which
can result in programming time of less than one minute.
This MTP EPROMTM is packaged in industry standard 32
pin dual-in-line packages, 32 lead PLCC, 32 lead SOP
and 32 lead TSOP packages.
PIN CONFIGURATIONS
32 PDIP/SOP
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32 TSOP
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
A11
A9
A8
A13
A14
A17
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX26C2000B
32 PLCC
4
A7 5
1 32
30
29 A14
A6 A13
A5 A8
A4 A9
A3 9 MX26C2000B 25 A11
A2 OE
A1 A10
A0 CE
Q0 13
14
21 Q7
17 20
PIN DESCRIPTION
32 OE
31 A10
30 CE
29 Q7
28 Q6
27 Q5
26 Q4
25 Q3
24 GND
23 Q2
22 Q1
21 Q0
20 A0
19 A1
18 A2
17 A3
SYMBOL
A0~A17
Q0~Q7
CE
OE
WE
VPP
NC
VCC
GND
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Program Supply Voltage
No Internal Connection
Power Supply Pin (+5V)
Ground Pin
P/N: PM0765
1 REV. 0.8, NOV. 20, 2002
1 page  
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each of the eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
OUTPUT DISABLE
Output is disabled when OE is at logre high. When in
output disabled all circuitry is enabled. Except the output
pins are in a high impedance state(TRI-ATATE).
MX26C2000B
Table 1: BUS OPERATIONS
Mode
READ-ONLY
MODE
COMMAND
MODE
Read
Output Disable
Standby
Manufacturer Identification
Device Identification
Read
Output Disable
Standby(4)
Program
VPP(1) A0 A9 CE OE WE Q0~Q7
VPPL A0 A9 VIL VIL VIH Data Out
VPPL X X
VIL VIH VIH Tri-State
VPPL X X VIH X X Tri-State
VPPL VIL VID(2) VIL VIL VIH Data=C2H
VPPL VIH VID(2) VIL VIL VIH Data=C3H
VPPH A0 A9 VIL VIL VIH Data Out(3)
VPPH X X
VIL VIH VIH Tri-State
VPPH X X(5) VIH X X Tri-State
VPPH A0 A9 VIL VIH VIL Data Inb
Note:
1. Refer to DC Characteristics. When VPP=VPPL memory contents can be read but not written or erased.
2. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
3. Read operations with VPP=VPPH may access array data or the intelligent identifier codes.
4. With VPP at high voltage the standby current equals ICC+IPP(standby).
5. Refer to Table 2 for vaild data-in during a write operation.
6. X can be VIL or VIH.
P/N: PM0765
5 REV. 0.8, NOV. 20, 2002
5 Page 
MX26C2000B
AC RAED CHARACTERISTICS OVER OPERATING RANGE WITH VPP=VCC
Symbol Parameter
90 100 120 150 Unit
Jeded STD
MIN MAX MIN MAX MIN MAX MIN MAX
tAVAV TRC Read Cycle Time
90 100 120 150 ns
tELQV TCE CE Access Time
0 90 0 100 0 120 0 150 ns
tAVQV TACC Address Access Time
0 90 0 100 0 120 0 150 ns
tGLQV TOE OE Access Time
0 40 0 45 0 50 0 65 ns
tELQX TLZ CE to Output in Low Z(Note 1) 0 0 0 0 ns
tEHQZ TDF Chip Disable to Output in High Z(Note 2) 0 30 0 35 0 35 0 50 ns
tGLQX TOLZ OE to Output in Low Z (Note 1)
0
0
0
0 ns
tGHQZ TDF Output Disable to Output in High Z
0 30 0 35 0 35 0 50 ns
(Note 1)
tAXQX TOH Output Hold from Address, CE or OE,
0
0
0 0 ns
change
tWHGL TWHGL Write Recovery Time Before Read
6
6
6
6 us
tVCS TVCS VCC Setup Time to Valid Read (Note 2)
50
50
50 50 us
Note:
1. Sampled: not 100% tested.
2. Guaranteed by design. not tested.
P/N: PM0765
11 REV. 0.8, NOV. 20, 2002
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MX26C2000B.PDF ] | |
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