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PDF LTC2436-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC2436-1 | |
| Descripción | 2-Channel Differential Input 16-Bit No Latency DS ADC | |
| Fabricantes | Linear Technology | |
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LTC2436-1
2-Channel Differential Input
16-Bit No Latency ∆Σ ADC
FEATURES
s 2-Channel Differential Input with Automatic
Channel Selection (Ping-Pong)
s Low Supply Current: 200µA, 4µA in Autosleep
s Differential Input and Differential Reference with
GND to VCC Common Mode Range
s 0.12LSB INL, No Missing Codes
s 0.16LSB Full-Scale Error and 0.006LSB Offset
s 800nV RMS Noise, Independent of VREF
s No Latency: Digital Filter Settles in a Single Cycle and
Each Channel Conversion is Accurate
s Internal Oscillator—No External Components
Required
s 87dB Min, 50Hz and 60Hz Notch Filter
s Narrow SSOP-16 Package
s Single Supply 2.7V to 5.5V Operation
s Pin Compatible with the 24-Bit LTC2412
U
APPLICATIO S
s Direct Sensor Digitizer
s Weight Scales
s Direct Temperature Measurement
s Gas Analyzers
s Strain-Gage Transducers
s Instrumentation
s Data Acquisition
s Industrial Process Control
DESCRIPTIO
The LTC®2436-1 is a 2-channel differential input mi-
cropower 16-bit No Latency ∆ΣTM analog-to-digital con-
verter with an integrated oscillator. It provides 0.5LSB
INL and 800nV RMS noise independent of VREF. The two
differential channels convert alternately with a channel
identification included in the conversion result. It uses
delta-sigma technology and provides single conversion
settling of the digital filter. Through a single pin, the
LTC2436-1 can be configured for better than 87dB input
differential mode rejection at 50Hz and 60Hz ±2%, or it
can be driven by an external oscillator for a user defined
rejection frequency. The internal oscillator requires no
external frequency setting components.
The converter accepts any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The full-
scale differential input range is from – 0.5 •␣ VREF to 0.5 •
VREF. The reference common mode voltage, VREFCM, and
the input common mode voltage, VINCM, may be indepen-
dently set anywhere between GND and VCC. The DC
common mode input rejection is better than 140dB.
The LTC2436-1 communicates through a flexible 3-wire
digital interface which is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
TYPICAL APPLICATIO
5V REF
4.9k
(100mV)
100Ω
THERMOCOUPLE
1µF
1
VCC
2 REF+
4 CH0+
14
FO
LTC2436-1
5 CH0–
13
SCK
3 REF–
12
SDO
6 CH1+
7 CH1–
8, 9, 10, 15, 16
GND
11
CS
24361 TA01
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
3-WIRE
SPI INTERFACE
Effective Resolution vs VREF
90
80
70
60
50
40
30
20
10
0
0 1 2 345
VREF (V)
24361 TA02
*COMBINES EFFECTS OF PEAK-TO-PEAK NOISE
AND 16-BIT STEP SIZE (VREF/216)
24361f
1
1 page  
LTC2436-1
WU
TI I G CHARACTERISTICS The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
fEOSC
tHEO
tLEO
tCONV
fISCK
DISCK
fESCK
tLESCK
tHESCK
tDOUT_ISCK
tDOUT_ESCK
t1
t2
t3
t4
tKQMAX
tKQMIN
t5
t6
PARAMETER
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
Internal SCK Frequency
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 19-Bit Data Output Time
External SCK 19-Bit Data Output Time
CS ↓ to SDO Low Z
CS ↑ to SDO High Z
CS ↓ to SCK ↓
CS ↓ to SCK ↑
SCK ↓ to SDO Valid
SDO Hold After SCK ↓
SCK Set-Up Before CS ↓
SCK Hold After CS ↓
CONDITIONS
FO = 0V
External Oscillator (Note 10)
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
(Note 9)
(Note 8)
(Note 8)
(Note 8)
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
(Note 8)
(Note 9)
(Note 8)
(Note 5)
MIN TYP MAX UNITS
q 2.56
2000 kHz
q 0.25
390 µs
q 0.25
390 µs
q 143.8
146.7 149.6
q 20510/fEOSC (in kHz)
17.5
fEOSC/8
q 45
55
ms
ms
kHz
kHz
%
q 2000 kHz
q 250
ns
q 250
ns
q 1.06
1.09 1.11
q 152/fEOSC (in kHz)
q 19/fESCK (in kHz)
q0
200
ms
ms
ms
ns
q0
200 ns
q0
200 ns
q 50
ns
q 220 ns
q 15
ns
q 50
ns
q 50 ns
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–,
VINCM = (IN+ + IN–)/2, IN+ and IN– are defined as the selected positive
(CH0+ or CH1+) and negative (CH0– or CH1–) input respectively.
Note 4: FO pin tied to GND or to an external conversion clock source
with fEOSC = 139,800Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a precise analog input voltage. Maximum specifications are limited by
the LSB step size (VREF/216) and the single shot measurement. Typical
specifications are measured from the center of the quantization band.
Note 7: FO = GND (internal oscillator) or fEOSC = 139,800Hz ±2%
(external oscillator).
Note 8: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 9: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator.
FO = 0V.
Note 12: 800nV RMS noise is independent of VREF. Since the noise
performance is limited by the quantization, lowering VREF improves the
effective resolution.
Note 13: Guaranteed by design and test correlation.
Note 14: The low sleep mode current is valid only when CS is high.
24361f
5
5 Page 
LTC2436-1
APPLICATIO S I FOR ATIO
Table 2. LTC2436-1 Output Data Format
Differential Input Voltage
VIN*
VIN* ≥ 0.5 • VREF**
0.5 • VREF** – 1LSB
0.25 • VREF**
0.25 • VREF** – 1LSB
0
Bit 18
EOC
0
0
0
0
0
Bit 17
CH0/CH1
0/1
0/1
0/1
0/1
0/1
Bit 16
SIG
1
1
1
1
1
–1LSB
0 0/1 0
– 0.25 • VREF**
0 0/1
– 0.25 • VREF** – 1LSB
0 0/1
– 0.5 • VREF**
0 0/1
VIN* < –0.5 • VREF**
0 0/1
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
0
0
0
0
Bit 15
MSB
1
0
0
0
0
1
1
1
1
0
Bit 14
0
1
1
0
0
1
1
0
0
1
Bit 13
0
1
0
1
0
1
0
1
0
1
Bit 12
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
…
Bit 0
0
1
0
1
0
1
0
1
0
1
–80
–90
–100
–100
–120
–130
–140
48 50 52 54 56 58 60 62
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
24361 F04
Figure 4. LTC2436-1 Normal Mode
Rejection When Using an Internal Oscillator
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12 –8 –4 0 4 8 12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
24361 F05
Figure 5. LTC2436-1 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Simultaneous Frequency Rejection
The LTC2436-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2Hz as shown in Figure 4. For this simultaneous 50Hz/
60Hz rejection, FO should be connected to GND.
When a fundamental rejection frequency different from
the range 49Hz to 61.2Hz is required or when the converter
must be sychronized with an outside source, the LTC2436-1
can operate with an external conversion clock. The conveter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz to be detected. The external clock signal duty cycle
is not significant as long as the minimum and maximum
specifications for the high and low periods, tHEO and tLEO,
are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2436-1 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4%. The normal mode rejection as a function of the input
frequency deviation from fEOSC/2560 is shown in Figure 5.
24361f
11
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| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2436-1.PDF ] | |
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