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PDF ICS843256 Data sheet ( Hoja de datos )
| Número de pieza | ICS843256 | |
| Descripción | CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843256
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
GENERAL DESCRIPTION
The ICS843256 is a Crystal-to-3.3V LVPECL
ICS Clock Synthesizer/Fanout Buffer designed for
HiPerClockS™ Fibre Channel and Gigabit Ethernet applications
and is a member of the HiperClockS™ family of
High Performance Clock Solutions from ICS. The
output frequency can be set using the frequency select
pins and a 25MHz crystal for Ethernet frequencies, or a
19.44MHz crystal for SONET. The low phase noise charac-
teristics of the ICS843256 make it an ideal clock for these
demanding applications.
FEATURES
• Six LVPECL outputs
• Crystal oscillator interface
• Output frequency range: 53.125MHz to 333.3333MHz
• Crystal input frequency range: 25MHz to 33.333MHz
• RMS phase jitter at 125MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.33ps (typical)
• Full 3.3V or 3.3V core, 2.5V output supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
SELECT FUNCTION TABLE
Inputs
FB_SEL N_SEL1 N_SEL0
00 0
00
1
0 10
011
10
0
10
1
110
11 1
M Divide
25
25
25
25
32
32
32
32
Function
N Divide
1
2
4
5
1
2
4
8
• Available in both standard and lead-free RoHS-compliant
packages
M/N
25
12.5
6.25
5
32
16
8
4
BLOCK DIAGRAM
PLL_BYPASS Pullup
XTAL_IN
XTAL_OUT
OSC
FB_SEL Pulldown
N_SEL1 Pullup
Pullup
N_SEL0
1 Output
PLL Divider
0
Feedback
Divider
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
VCCO
VCCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
PLL_BYPASS
VCCA
VCC
FB_SEL
1
2
3
4
5
6
7
8
9
10
11
12
24 Q3
23 nQ3
22 Q4
21 nQ4
20 Q5
19 nQ5
18 N_SEL1
17 VEE
16 VEE
15 N_SEL0
14 XTAL_OUT
13 XTAL_IN
Q3 ICS843256
24-Lead, 300-MIL SOIC
nQ3 7.5mm x 15.33mm x 2.3mm
body package
Q4 M Package
Top View
nQ4 24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
Q5 body package
G Package
nQ5 Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843256AM
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 29, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843256
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TABLE
4D.
LVPECL
DC
CHARACTERISTICS,
V
CC
=
V
CCA
=
3.3V±5%,
V
CCO
=
3.3V±5%
OR
2.5V±5%,
TA
=
0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V Output High Voltage; NOTE 1
OH
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
V - 1.4
CCO
VCCO - 2.0
0.6
V - 0.9
CCO
VCCO - 1.7
1.0
Units
V
V
V
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
15.625
25.5
50
7
1
Units
MHz
Ω
pF
mW
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
FOUT
tjit(Ø)
Output Frequency
RMS Phase Jitter (Random)
125MHz, Integration Range:
1.875MHz - 20MHz
53.125
0.33
tsk(o) Output Skew; NOTE 1, 2
TBD
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
50
tLOCK
PLL Lock Time
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
333.33
1
Units
MHz
ps
ps
ps
%
ms
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
FOUT
tjit(Ø)
Output Frequency
RMS Phase Jitter (Random)
125MHz, Integration Range:
1.875MHz - 20MHz
53.125
0.32
tsk(o) Output Skew; NOTE 1, 2
TBD
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
TBD
50
tLOCK
PLL Lock Time
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
333.33
1
Units
MHz
ps
ps
ps
%
ms
843256AM
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 29, 2005
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS843256
FEMTOCLOCKS™CRYSTAL-TO-3.3V LVPECL
FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7A. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
0
50°C/W
200
43°C/W
500
38°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 7B. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA by Velocity (Meters per Second)
Multi-Layer PCB, JEDEC Standard Test Boards
0
70°C/W
1
65°C/W
2.5
62°C/W
TRANSISTOR COUNT
The transistor count for ICS843256 is: 3863
843256AM
www.icst.com/products/hiperclocks.html
11
REV. A NOVEMBER 29, 2005
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ICS843256.PDF ] | |
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