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Número de pieza | FM8P51 | |
Descripción | EPROM/ROM-Based 8-Bit Microcontroller | |
Fabricantes | Feeling | |
Logotipo | ||
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FEELING
TECHNOLOGY
FM8P51
EPROM/ROM-Based 8-Bit Microcontroller
Devices Included in this Data Sheet:
‧ FM8P51E : EPROM device
‧ FM8P51 : Mask ROM device
FEATURES
‧ Only 47 single word instructions
‧ All instructions are single cycle except for program branches which are two-cycle
‧ 13-bit wide instructions
‧ 8-bit wide data path
‧ 5-level deep hardware stack
‧ 4K x 13 bits on chip EPROM/ROM
‧ 140 x 8 bits on chip general purpose registers (SRAM)
‧ Operating speed: DC-20 MHz clock input
DC-100 ns instruction cycle
‧ Direct, indirect addressing modes for data accessing
‧ One 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler
‧ Three 8-bit real time clock/counter (Timer1, Timer2, and Timer3) with period setting
‧ Internal Power-on Reset (POR)
‧ Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)
‧ Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)
‧ On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog
enable/disable control
‧ Five I/O ports (38 I/O pins) with independent direction control
‧ 32 programmable pull-high input pins
‧ 12 wake-up pins
‧ 2 open-drain pins
‧ 2 R-option pins
‧ Clock output with high driving ability
‧ 19 channels of 15-bit resolution Resistor to Frequency Converter (RFC) output
‧ 2 channels of maximum 10-bit resolution Pulse Width Modulation (PWM) output
‧ Built-in 8-bit data comparator
‧ Seven internal interrupt source: Timer0 overflow, Timer1 match, Timer2 match, Timer3 match, SPI module
(Receive & Transmit), RFC module; One external interrupt source: INT pin change
‧ Wake-up from SLEEP by port input change
‧ Power saving SLEEP mode
‧ Programmable Code Protection
‧ Built-in RC oscillator with external resistor
‧ Selectable oscillator options:
- ERC: External Resistor/Capacitor Oscillator
- ERIC: External Resistor/Internal Capacitor Oscillator
- HF: High Frequency Crystal/Resonator Oscillator
- LF: Low Frequency Crystal Oscillator
‧ Wide-operating voltage range:
- EPROM : 2.3V to 5.5V
- ROM : 2.3V to 5.5V
This datasheet contains new product information. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Rev1.2 Mar 15, 2005
P.1/FM8P51
1 page FEELING
TECHNOLOGY
FM8P51
1.0 MEMORY ORGANIZATION
FM8P51 series memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8P51 series have an 12-bit Program Counter capable of addressing a 4K×13 program memory space.
The RESET vector for the FM8P51 series is at FFFh.
The H/W interrupt vector is at 001h. And the S/W interrupt vector is at 002h.
FM8P51 series has program memory size greater than 1K words, but the CALL and GOTO instructions only have a
10-bit address range. This 10-bit address range allows a branch within a 1K program memory page size. To allow
CALL and GOTO instructions to address the entire 4K program memory address range for FM8P51 series, there is
another two bits to specify the program memory page. This paging bit comes from the PG<1:0> bits (STATUS<6:5>).
When doing a CALL or GOTO instruction, the user must ensure that page bit PG<1:0> are programmed so that the
desired program memory page is addressed. When one of the return instructions is executed, the entire 12-bit PC is
POPed from the stack. Therefore, manipulation of the PG <1:0> is not required for the return instructions.
FIGURE 1.1: Program Memory Map and STACK
PC<11:0>
FFFh
Stack 1
Stack 2
Stack 3
Stack 4
Stack 5
Reset Vector
:
:
002h S/W Interrupt Vector
001h H/W Interrupt Vector
000h
FM8P51 Series
Rev1.2 Mar 15, 2005
P.5/FM8P51
5 Page FEELING
TECHNOLOGY
FM8P51
2.1.4 STATUS (Status Register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
03h (r/w) STATUS
GP
PG1
PG0
TO
PD
Z
DC
C
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the
STATUS Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
ADDAR, ADDIA
= 1, a carry occurred.
= 0, a carry did not occur.
SUBAR, SUBIA
= 1, a borrow did not occur.
= 0, a borrow occurred.
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
DC : Half carry/half borrow bit.
ADDAR, ADDIA
= 1, a carry from the 4th low order bit of the result occurred.
= 0, a carry from the 4th low order bit of the result did not occur.
SUBAR, SUBIA
= 1, a borrow from the 4th low order bit of the result did not occur.
= 0, a borrow from the 4th low order bit of the result occurred.
Z : Zero bit.
= 1, the result of a logic operation is zero.
= 0, the result of a logic operation is not zero.
PD : Power down flag bit.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
TO : Time overflow flag bit.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
= 0, a watch-dog time overflow occurred.
PG1:PG0 : Program memory page select bits. Used for GOTO, CALL, or any instruction with PCL as destination.
PG1
PG0
Program Memory Page [Address]
00
Page 0 [000h~3FFh]
01
Page 1 [400h~7FFh]
10
Page 2 [800h~BFFh]
11
Page 3 [C00h~FFFh]
GP : General purpose read/write bit.
Rev1.2 Mar 15, 2005
P.11/FM8P51
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet FM8P51.PDF ] |
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