PDF AM29PDS322D Data sheet ( Hoja de datos )

Número de pieza	AM29PDS322D
Descripción	Simultaneous Read/Write Page-Mode Boot Sector Flash Memory
Fabricantes	AMD
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No Preview Available ! www.DataSheet4U.com Am29PDS322D Data Sheet The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Publication Number 23569 Revision A Amendment 5 Issue Date December 4, 2006 1 page DATA SHEET TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Special Handling Instructions for FBGA Package .................... 5 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8 Table 1. Am29PDS322D Device Bus Operations .............................8 Requirements for Reading Array Data ..................................... 8 Read Mode ............................................................................... 8 Random Read (Non-Page Mode Read) ............................................8 Page Mode Read ...................................................................... 9 Table 2. Page Word Mode ................................................................9 Writing Commands/Command Sequences .............................. 9 Accelerated Program Operation ........................................................9 Autoselect Functions .........................................................................9 Simultaneous Read/Write Operations with Zero Latency ......... 9 Standby Mode .......................................................................... 9 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 10 Output Disable Mode .............................................................. 10 Table 3. Am29PDS322DT Top Boot Sector Addresses ..................11 Table 4. Am29PDS322DT Top Boot SecSi Sector Address ...........12 Table 5. Am29PDS322DB Bottom Boot Sector Addresses ............12 Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address . . .14 Autoselect Mode..................................................................... 15 Table 7. Autoselect Codes (High Voltage Method) ........................15 Sector/Sector Block Protection and Unprotection .................. 16 Table 8. Top Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................16 Table 9. Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................................16 Write Protect (WP#) ................................................................ 17 Temporary Sector/Sector Block Unprotect ............................. 17 Figure 1. Temporary Sector Unprotect Operation........................... 17 Figure 2. Temporary Sector Group Unprotect Operation................ 18 Figure 3. In-System Sector Group Protect/Unprotect Algorithms ... 19 SecSi (Secured Silicon) Sector Flash Memory Region .......... 20 Factory Locked: SecSi Sector Programmed and Protected at the Factory ..................................................................................20 Hardware Data Protection ...................................................... 20 Low VCC Write Inhibit .......................................................................20 Write Pulse “Glitch” Protection ........................................................21 Logical Inhibit ..................................................................................21 Power-Up Write Inhibit ....................................................................21 Command Definitions . . . . . . . . . . . . . . . . . . . . . 21 Reading Array Data ................................................................ 21 Reset Command ..................................................................... 21 Autoselect Command Sequence ............................................ 21 Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 22 Word Program Command Sequence ..................................... 22 Unlock Bypass Command Sequence ..............................................22 Chip Erase Command Sequence ........................................... 22 Figure 4. Unlock Bypass Algorithm................................................. 23 Figure 5. Program Operation .......................................................... 23 Sector Erase Command Sequence ........................................ 24 Erase Suspend/Erase Resume Commands ........................... 24 Figure 6. Erase Operation.............................................................. 25 Am29PDS322D Command Definitions . . . . . . . . 26 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 27 DQ7: Data# Polling ................................................................. 27 Figure 7. Data# Polling Algorithm .................................................. 27 RY/BY#: Ready/Busy#............................................................ 28 DQ6: Toggle Bit I .................................................................... 28 Figure 8. Toggle Bit Algorithm........................................................ 28 DQ2: Toggle Bit II ................................................................... 29 Reading Toggle Bits DQ6/DQ2 ............................................... 29 DQ5: Exceeded Timing Limits ................................................ 29 DQ3: Sector Erase Timer ....................................................... 29 Table 11. Write Operation Status ................................................... 30 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31 Figure 9. Maximum Negative Overshoot Waveform ...................... 31 Figure 10. Maximum Positive Overshoot Waveform...................... 31 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 31 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) .............................................................................. 33 Figure 12. Typical ICC1 vs. Frequency ............................................ 33 Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 13. Test Setup.................................................................... 34 Table 12. Test Specifications ......................................................... 34 Key to Switching Waveforms. . . . . . . . . . . . . . . . 34 Figure 14. Input Waveforms and Measurement Levels ................. 34 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 15. Conventional Read Operation Timings ......................... 35 Figure 16. Page Mode Read Timings ............................................ 36 Hardware Reset (RESET#) .................................................... 37 Figure 17. Reset Timings ............................................................... 37 Erase and Program Operations .............................................. 38 Figure 18. Program Operation Timings.......................................... 39 Figure 19. Accelerated Program Timing Diagram.......................... 39 Figure 20. Chip/Sector Erase Operation Timings .......................... 40 Figure 21. Back-to-back Read/Write Cycle Timings ...................... 41 Figure 22. Data# Polling Timings (During Embedded Algorithms). 41 Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 42 Figure 24. DQ2 vs. DQ6................................................................. 42 Temporary Sector Unprotect .................................................. 43 Figure 25. Temporary Sector Group Unprotect Timing Diagram ... 43 Figure 26. Sector Group Protect and Unprotect Timing Diagram .. 44 Alternate CE# Controlled Erase and Program Operations ..... 45 Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings.......................................................................... 46 Erase And Programming Performance. . . . . . . . 47 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 47 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48 FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 12 mm package ................................................................ 48 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49 December 4, 2006 23569A5 Am29PDS322D 3 5 Page DATA SHEET Page Mode Read The device is capable of fast Page mode read and is compatible with the Page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 4 words. The appropriate Page is selected by the higher address bits A20–A2 and the LSB bits A1–A0 determine the specific word within that page. This is an asynchronous operation with the micropro- cessor supplying the specific word location. The random or initial page access is equal to tACC or tCE and subsequent Page read accesses (as long as the locations specified by the microprocessor falls within that Page) are equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Here again, CE# selects the device and OE# is the output control and should be used to gate data to the output pins if the device is se- lected. Fast Page mode accesses are obtained by keeping A2–A20 constant and changing A0 to A1 to select the specific word within that page. See Figure 16 for timing specifications. The following table determines the specific word within the selected page: Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the ACC pin returns the device to normal op- eration. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Table 2. Page Word Mode Word A1 Word 0 0 Word 1 0 Word 2 1 Word 3 1 A0 0 1 0 1 Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. December 4, 2006 23569A5 Am29PDS322D 9 11 Page

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