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PDF CY7B9950 Data sheet ( Hoja de datos )

Número de pieza CY7B9950
Descripción High-Speed Multi-Phase PLL Clock Buffer
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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RoboClock
CY7B9950
2.5/3.3V, 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
Features
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 100 ps
• Cycle-cycle jitter < 100 ps
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
Eight LVTTL outputs driving 50terminated lines
LVCMOS/LVTTL over-voltage-tolerant reference input
Phase adjustments in 625-/1250-ps steps up to +7.5 ns
2x, 4x multiply and (1/2)x, (1/4)x divide ratios
Spread-Spectrum-compatible
Industrial temp. range: 40°C to +85°C
32-pin TQFP package
Description
The CY7B9950 RoboClockis a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
Block Diagram
Pin Configuration
TEST PE/HD FS VDDQ1
REF
FB
1F1:0
2F1:0
3F1:0
4F1:0
33
PLL
3
3 Phase
3 Select
3 Phase
3 Select
3 Phase
Select
3 and /K
3 Phase
Select
3 and /M
1Q0
1Q1
2Q0
2Q1
3F1
4F0
4F1
PE/HD
VDDQ4
4Q1
4Q0
VSS
1
2
3
4
5
6
7
8
CY7B9950
24 1F1
23 1F0
22 sOE#
21 VDDQ1
20 1Q0
19 1Q1
18 VSS
17 VSS
3Q0
3Q1
VDDQ3
4Q0
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07338 Rev. *B
Revised March 4, 2003

1 page




CY7B9950 pdf
RoboClock
CY7B9950
DC Specifications @ 3.3V
Parameter
Description
Condition
Min.
Max. Unit
VDD
VIL
VIH
VIHH[9]
VIMM[9]
VILL[9]
IIL
I3
IPU
IPD
VOL
VOH
IDDQ
3.3 Operating Voltage 3.3V ± 10%
2.97 3.63 V
Input LOW Voltage
REF, FB and sOE# Inputs
0.8 V
Input HIGH Voltage
2.0 V
Input HIGH Voltage
Input MID Voltage
Input LOW Voltage
3-Level Inputs
VDD 0.6
(TEST, FS, nF[1:0], PE/HD) (These pins are normally
wired to VDD,GND or unconected.)
VDD/2 0.3 VDD/2 + 0.3
0.6
V
V
V
Input Leakage Current VIN = VDD/GND,VDD = max. (REF and FB inputs)
3-Level Input DC Current HIGH, VIN = VDD
MID, VIN = VDD/2
LOW, VIN = VSS
3-Level Inputs
(TEST, FS, nF[1:0],
DS[1:0], PD#/DIV, PE/HD)
Input Pull-up Current
VIN = VSS, VDD = max.
Input Pull-down Current VIN = VDD, VDD = max., (sOE#)
Output LOW Voltage
IOL = 12 mA (PE/HD = L/H), (nQ[0:1])
IOL = 24 mA (PE/HD = MID),(nQ[0:1])
Output HIGH Voltage IOH = 12 mA (PE/HD = L/H),(nQ[0:1])
IOH = 24 mA (PE/HD = MID),(nQ[0:1])
Quiescent Supply Current
VDD = max., TEST =
outputs not loaded
MID, REF
= LOW, sOE#
= LOW,
5
50
200
100
2.4
2.4
5 µA
200 µA
50 µA
µA
µA
100 µA
0.4 V
0.4 V
V
V
2 mA
IDD Dynamic Supply Current @ 100 MHz
CIN Input Pin Capacitance
230 mA
4 pF
AC Test Loads and Waveforms
VDDQ
Output
20pF
Output
150Ω
150Ω
20pF
For Lock Output
tORISE
tOFALL
For All Other Outputs
tORISE
tOFALL
2.0V
VTH =1.5V
0.8V
tPWL
tPWH
1.7V
VTH =1.25V
0.7V
tPWL
tPWH
3.3V LVTTL OUTPUT WAVEFORM
1 ns
1 ns
3.0V
2.0V
VTH=1.5V
0.8V
0V
3.3V LVTTL INPUT TEST WAVEFORM
Document #: 38-07338 Rev. *B
2.5V LVTTL OUTPUT WAVEFORM
1 ns
1 ns
2.5V
1.7V
VTH=1.25V
0.7V
0V
2.5V LVTTL INPUT TEST WAVEFORM
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