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PDF MTL003 Data sheet ( Hoja de datos )
| Número de pieza | MTL003 | |
| Descripción | SXGA Flat Panel Controller | |
| Fabricantes | Myson | |
| Logotipo |  |
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MYSON
TECHNOLOGY
MTL003
(Rev. 0.95)
SXGA Flat Panel Controller
FEATURES
General
• Auto configuration of sampling clock frequency, phase, H/V center, as well as white balance.
• Auto detection of present or non-present or over range sync signals and their polarities.
• Composite sync separation and odd/even field detection of interlaced video.
• On-chip output PLL provide clock frequency fine-tune (inverse, duty cycle and delay).
• Selection of serial 2-wire I2C or 8-bit direct host interface to 8-bit MCU.
• 3.3V supplier, 5V I/O tolerance in 256-pin PQFP or 272-pin BGA package.
Input Processor
• Single RGB (24-bit) or Dual RGB (48-bit) input rates up to 160MHz.
• Support both non-interlaced and interlaced RGB graphic input signals.
• YUV 4:2:2 or YUV 4:1:1 (CCIR601) interlaced video input.
• Glue-less connection to Philips SAA711x digital video decoder.
• Built-in YUV to RGB color space converter.
• Compliant with digital LVDS/PanelLink TMDS input interface.
• PC input resolution up to SXGA 1280x1024 @85Hz.
Video Processor
• Independent programmable Horizontal and Vertical scaling ratios from 1/32 to 32
• Flexible de-interlacing unit for digital YUV video input data.
• Zoom to full screen resolution of de-interlaced YUV video data stream.
• Built-in programmable gain control for white balance alignments.
• Built-in programmable 8-bit or 10-bit gamma correction table.
• Built-in programmable temporal color dithering.
• Built-in programmable interpolation look-up table.
• Support smooth panning under viewing window change.
Output Processor
• Single pixel (18/24-bit) or Dual pixel (36/48-bit) per clock digital RGB output.
• Built-in output timing generator with programmable clock and H/V sync.
• Support VGA/SVGA/XGA/SXGA display resolution.
• Overlay input interface with external OSD controller.
• Double scan capability for interlaced input.
Memory Interface
• Support 48/32/24 bit bus width, SDRAM/SGRAM x2 or x3 configuration.
• Optional display through internal line buffer without external frame-buffer memory.
• Support power down mode.
GENERAL DESCRIPTION
The MTL003 Flat Panel Display (FPD) Controller is an input format converter for TFT-LCD Monitor or LCD
TV application which accepts 15-pin D-sub RGB graphic signals (through ADC), YUV signals from digital
video decoder or digital RGB graphic signals from PanelLink TMDS receiver. It includes a RGB/YUV input
processor, configurable frame-buffer memory interface, video scaling up/down processor, OSD input
interface and output display processor in 256-pin PQFP or 272-pin BGA package.
Revision 0.95
-1-
2000/06/14
1 page  
MYSON
TECHNOLOGY
MTL003
(Rev. 0.95)
MD[47:40]
MD[39:32]
MD[31:24]
MD[23:16]
MD[15:8]
MD[7:0]
I/O 151-158 Memory Blue (B1) data
I/O 170-177 Memory Green (G1) data
I/O 211-218 Memory Red (R1) data
I/O 140-147 Memory Blue (B0) data
I/O 160-167 Memory Green (G0) data
I/O 202-209 Memory Red (R0) data
Host Interface
Name
RST#
AD[7:0]
HWR#
HRD#
ALE
HCS#
BUSSEL
IRQ
Type
I
I/O
I
I
I
I
I
O
Pin#
235
227-220
232
233
230
228
236
237
Description
System reset input, active low.
The address and data bus of 8-bit direct interface or
2-wire I2C series bus
Bit 1: SDA, serial bus data
Bit 0: SCK, serial bus clock
Host write strobe, active low
Host read strobe, active low
Host address latch enable for 8-bit direct bus
Host chip select
Bus mode selection. 0: I2C bus, 1: 8-bit direct bus
Interrupt request output
OSD Interface
Name
OCLK
OVSYNC
OHSYNC
OSDRED
OSDGRN
OSDBLU
OSDINT
OSDEN
Type
O
O
O
I
I
I
I
I
Pin#
126
136
138
131
132
133
135
134
Description
Clock for external OSD
Vertical sync for external OSD
Horizontal sync for external OSD
OSD red input
OSD green input
OSD blue input
OSD intensity input
OSD overlay enable
Other Interface
Name
XI
XO
EXTDCLK
EXTMCLK
GPIO[7:0]
NC
Type
I
O
I
I
I/O
-
Pin#
61
60
246
234
238-245
254
Description
Oscillator frequency input
Oscillator frequency output
External display clock input
External memory clock input
General purpose I/O or
Bit 7: ADVS, Vertical sync for A/D converter
Bit 6: ADHS, Horizontal sync for A/D converter
Bit 2: MA9_SGRAM, Memory address 9 for SGRAM
Bit 0: RAWHS/SOG, Input source HSYNC or
Input Sync On Green
Default: Bit[7:2]: Output direction
Bit[1:0]: Input direction
No connection
3.3V Power and Ground
Name
Pin#
DVDD
19, 30, 92, 121, 139, 159, 179, 201
DVSS
10, 28, 95, 112, 137, 150, 169, 200
PVDD
1, 48, 64, 83, 125, 129, 192, 210, 229, 252
PVSS
39, 57, 65, 66, 127, 128, 130, 181, 193, 194,
Description
Digital power 3.3V
Digital ground
Pad power 3.3V
Pad ground
Revision 0.95
-5-
2000/06/14
5 Page 
MYSON
TECHNOLOGY
MTL003
(Rev. 0.95)
3.3 Output Processor
General Description
Output processor provides the interface for both LCD panel and OSD controller. MTL003 can work for frame-
buffer or non-frame-buffer mode. When in frame-buffer mode, there is no restriction between the timing of
input and output. When in non-frame-butter mode, output frame rate must be equal to input frame rate and
output display time must be equal to input display time due to the absence of frame buffer. Some features
based on using the frame buffer do not work in non-frame-buffer mode, for example the screen write, static
mode in de-interlace etc.
3.3.1 Display Timing Generation
There are three display timing modes:
¨ Frame-buffer Mode: is used for frame rate conversion. External frame buffer is needed.
¨ Non-frame-buffer Mode: performs a low cost version of solution where the external frame buffer is not
needed. This mode is used in the condition that output frame rate is equal to input frame; some features
are disabled in this mode.
¨ Frame SYNC Mode: is used for video input. In this mode, output frame is synchronized to input frame,
gives the moving picture a smooth change.
Frame Buffer Mode:
Input Frame
Output Frame
External Frame Buffer
Non Frame Buffer Mode
Input Frame
x
Lock point
Output Frame
Frame SYNC Mode
Input Frame
x
Lock point
Output Frame
Revision 0.95
External Frame Buffer
Fig. 3.2.3 Display Timing modes
- 11 -
2000/06/14
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MTL003.PDF ] | |
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