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PDF DS90UR241 Data sheet ( Hoja de datos )
| Número de pieza | DS90UR241 | |
| Descripción | (DS90UR124 / DS90UR241) DC-Balanced 24-Bit LVDS Serializer and Deserializer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
September 2006
DS90UR241/DS90UR124
5-43 MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS90UR241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream sim-
plifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and connector
size and pins.
The DS90UR241/124 incorporates LVDS signaling on the
high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the Serializer output edge rate
for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects. Using National Semiconductor’s proprietary
random lock, the Serializer’s parallel data are randomized to
the Deserializer without the need of REFCLK.
Features
n 5 MHz–43 MHz embedded clock and DC-Balanced 24:1
and 1:24 data transmission
n User defined pre-emphasis driving ability through
external resistor on LVDS outputs and capable to drive
up to 10 meters shielded twisted-pair cable
n User selectable clock edge for parallel data on both
Transmitter and Receiver
n Supports AC-coupling data transmission
n Individual power-down controls for both Transmitter and
Receiver
n 1.8V VCM at LVDS input side
n Embedded clock CDR (clock and data recovery) on
Receiver and no source of reference clock needed
n All codes RDL (random data lock) to support
hot-pluggable applications
n LOCK output flag to ensure data integrity at Receiver
side
n Balanced TSETUP/THOLD between RCLK and RDATA on
Receiver side
n Adjustable PTO (progressive turn-on) LVCMOS outputs
on Receiver to minimize EMI and SSO effects
n @Speed BIST to validate link integrity
n All LVCMOS inputs and control pins have internal
pulldown
n On-chip filters for PLLs on Transmitter and Receiver
n 48-pin TQFP package for Transmitter and 64-pin TQFP
package for Receiver
n Pure CMOS .35 µm process
n Power supply range 3.3V ± 10%
n Temperature range –40˚C to +105˚C
n Greater than 8 kV HBM ESD structure
n Meets ISO 10605 ESD compliance
n Backwards compatible with DS90C241/DS90C124
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation DS201945
20194501
www.national.com
1 page  
Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
tROS
tROH
tROS
tROH
tROS
tROH
tROS
tROH
tROS
tROH
tROS
tROH
tHZR
tLZR
tZHR
tZLR
tDD
ROUT (0:7) Setup Data to
RCLK (Group 1)
ROUT (0:7) Hold Data to
RCLK (Group 1)
ROUT (8:15) Setup Data to
RCLK (Group 2)
ROUT (8:15) Hold Data to
RCLK (Group 2)
ROUT (16:23) Setup Data
to RCLK (Group 3)
ROUT (16:23) Setup Data
to RCLK (Group 3)
ROUT (0:7) Setup Data to
RCLK (Group 1)
ROUT (0:7) Hold Data to
RCLK (Group 1)
ROUT (8:15) Setup Data to
RCLK (Group 2)
ROUT (8:15) Hold Data to
RCLK (Group 2)
ROUT (16:23) Setup Data
to RCLK (Group 3)
ROUT (16:23) Setup Data
to RCLK (Group 3)
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
PTOSEL = L,
(Figure 12)
PTOSEL = H,
(Figure 11)
PTOSEL = H,
(Figure 13)
PTOSEL = H,
(Figure 10)
ROUT[0:7]
ROUT [8:15],
LOCK
ROUT [16:23]
ROUT[0:7]
ROUT [8:15],
LOCK
ROUT [16:23]
ROUT [0:23],
RCLK, LOCK
RCLK
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.35)*
tRCP
(0.5*tRCP)–3 UI
(0.5*tRCP)–3 UI
(0.5*tRCP)–3 UI
(0.5*tRCP)–3 UI
(0.5*tRCP)–3 UI
(0.5*tRCP)–3 UI
(0.5*tRCP)–2 UI
(0.5*tRCP)+2 UI
(0.5*tRCP)−1 UI
(0.5*tRCP)+1 UI
(0.5*tRCP)+1 UI
(0.5*tRCP)–1 UI
3
3
3
3
[5+(5/56)]T+3.7
tDSR
Deserializer PLL Lock Time (Notes 5, 7)
5 MHz
from Powerdown
43 MHz
RxIN_TOL-L Receiver INput TOLerance (Notes 6, 9),
Left (Figure 16)
5 MHz–43 MHz
0.25
RxIN_TOL-R Receiver INput TOLerance (Notes 6, 9),
Right
(Figure 16)
5 MHz–43 MHz
0.25
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
[5+(5/56)]T
+8
128k*T
128k*T
ns
ns
ns
ns
ns
ms
ms
UI
UI
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for VDD = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: tDSR is the time required by the Deserializer to obtain lock when exiting powerdown mode.
Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the Deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: Guaranteed by Design (GBD) using statistical analysis.
Note 8: tJIT (@BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter.
Note 9: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 10: Figures 1, 2, 9, 10, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 11: Figures 6, 11, 12 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 12: TxOUT_E_O is affected by pre-emphasis value.
5 www.national.com
5 Page 
AC Timing Diagrams and Test Circuits (Continued)
20194513
FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing
FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
20194514
11 www.national.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet DS90UR241.PDF ] | |
Hoja de datos destacado
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| DS90UR241 | (DS90UR124 / DS90UR241) DC-Balanced 24-Bit LVDS Serializer and Deserializer | National Semiconductor |
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