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PDF CY7C1418AV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1418AV18 | |
| Descripción | (CY7C14xxAV18) 36-Mbit DDR-II SRAM 2-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRELIMINARY
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Features
• 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
• 250-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces
(data transferred at 500 MHz) @ 250 MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage (1.4V–VDD)
• 15 x 17 x 1.4 mm 1.0-mm pitch fBGA package,
165 ball (11x15 matrix)
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1416AV18 – 4M x 8
CY7C1427AV18 – 4M x 9
CY7C1418AV18 – 2M x 18
CY7C1420AV18 – 1M x 36
36-Mbit DDR-II SRAM 2-Word
Burst Architecture
Functional Description
The CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and
CY7C1420AV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry
and a 1-bit burst counter. Addresses for Read and Write are
latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read
data is driven on the rising edges of C and C if provided, or on
the rising edge of K and K if C/C are not provided. Each
address location is associated with two 8-bit words in the case
of CY7C1416AV18 and two 9-bit words in the case of
CY7C1427AV18 that burst sequentially into or out of the
device. The burst counter always starts with a “0” internally in
the case of CY7C1416AV18 and CY7C1427AV18. On
CY7C1418AV18 and CY7C1420AV18, the burst counter takes
in the least significant bit of the external address and bursts
two 18-bit words in the case of CY7C1418AV18 and two 36-bit
words in the case of CY7C1420AV18 sequentially into or out
of the device.
Asynchronous inputs include impedance match (ZQ).
Synchronous data outputs (Q, sharing the same physical pins
as the data inputs D) are tightly matched to the two output echo
clocks CQ/CQ, eliminating the need for separately capturing
data from each individual DDR SRAM in the system design.
Output data clocks (C/C) enable maximum system clocking
and data synchronization flexibility.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Shaded areas contain advance information.
250 MHz
250
TBD
200 MHz
200
TBD
167 MHz
167
TBD
Unit
MHz
mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document Number: 38-05616 Rev. **
Revised July 15, 2004
1 page  
Pin Configurations (continued)
PRELIMINARY
CY7C1418AV18 (2M × 18) – 15 × 17 FBGA
1234
5678
A
CQ NC/72M
A
R/W BWS1
K NC/144M LD
B NC DQ9 NC
A NC/288M K
BWS0
A
C NC NC NC VSS A A0 A VSS
D NC NC DQ10 VSS VSS VSS VSS VSS
E
NC
NC
DQ11
VDDQ
VSS
VSS
VSS VDDQ
F
NC DQ12 NC
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
NC DQ13 VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC DQ14 VDDQ
VDD
VSS
VDD
VDDQ
L NC DQ15 NC VDDQ VSS VSS VSS VDDQ
M NC NC
NC VSS
VSS VSS VSS VSS
N NC NC DQ16 VSS
A
A
A VSS
P
NC
NC DQ17
A
ACAA
R
TDO
TCK
A
A
AC
AA
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
CY7C1420AV18 (1M × 36) – 15 × 17 FBGA
1234
5678
9 10 11
A CQ NC/144M A
R/W BWS2
K
BWS1
LD
A NC/72M CQ
B
NC DQ27 DQ18
A
BWS3
K
BWS0
A
NC NC DQ8
C NC NC DQ28 VSS A A0 A VSS NC DQ17 DQ7
D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6
F
NC DQ30 DQ21 VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ5
G
NC DQ31 DQ22 VDDQ
VDD
VSS
VDD
VDDQ
NC
NC DQ14
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC DQ32 VDDQ
VDD
VSS
VDD
VDDQ
NC DQ13 DQ4
K
NC
NC DQ23 VDDQ
VDD
VSS
VDD
VDDQ
NC DQ12 DQ3
L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2
M
NC
NC
DQ34
VSS
VSS VSS VSS VSS
NC DQ11 DQ1
N NC DQ35 DQ25 VSS
A
A
A VSS NC NC DQ10
P
NC
NC DQ26
A
A C A A NC DQ9 DQ0
R
TDO
TCK
A
A
AC
AA
A
TMS
TDI
Document Number: 38-05616 Rev. **
Page 5 of 24
5 Page 
PRELIMINARY
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Write Cycle Descriptions[2, 8] (CY7C1420AV18) (continued)
BWS0 BWS1 BWS2 BWS3
HHH L
K
–
H H H H L-H
HHHH –
K Comments
L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is
written into the device. D[26:0] will remain unaltered.
– No data is written into the device during this portion of a Write operation.
L-H No data is written into the device during this portion of a Write operation.
Write Cycle Descriptions[2, 8](CY7C1427AV18)
BWS0
L
L
H
H
K K Comments
L-H – During the Data portion of a Write sequence,
the single byte (D[8:0]) is written into the device.
– L-H During the Data portion of a Write sequence,
the single byte (D[8:0]) is written into the device.
L-H – No data is written into the device during this portion of a Write operation.
– L-H No data is written into the device during this portion of a Write operation.
Document Number: 38-05616 Rev. **
Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet CY7C1418AV18.PDF ] | |
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