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PDF MC14534B Data sheet ( Hoja de datos )
| Número de pieza | MC14534B | |
| Descripción | 5 CASCADED BCD COUNTERS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
5 Cascaded BCD Counters
The MC14534B is composed of five BCD ripple counters that have their
respective outputs multiplexed using an internal scanner. Outputs of each
counter are selected by the scanner and appear on four (BCD) pins.
Selection is indicated by a logic high on the appropriate digit select pin. Both
BCD and digit select outputs have three–state controls providing an
“open–circuit” when these controls are high and allowing multiplexing.
Cascading may be accomplished by using the carry–out pin. The counters
and scanner can be independently reset by applying a high to the counter
master reset (MR) and the scanner reset (SR). The MC14534B was
specifically designed for application in real time or event counters where
continual updating and multiplexed displays are used.
• Four Operating Modes (See truth table)
• Input Error Detection Circuit
• Clock Conditioning Circuits for Slow Transition Inputs
• Counter Sequences on Positive Transition of Clock A
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MC14534B
L SUFFIX
CERAMIC
CASE 623
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
TO CAPACITORS
23
CLOCK B
CLOCK A
4
MASTER 2
RESET
5
MODE A
MODE B
6
PULSE
SHAPER
UNITS
C ÷ 10
Q0
Cn+4
Q3
OUTPUT
CONTROL
MUX
22 1
PULSE ERROR
DETECTOR
3
ERROR OUT
TEST
CONTROL
VDD = PIN 24
VSS = PIN 12
CARRY
CONTROL
TENS
C ÷ 10
Q0
Cn+4
Q3
HUNDREDS
C ÷ 10
Q0
Cn+4
Q3
MUX MUX
THOUSANDS
C ÷ 10
Q0
Cn+4
Q3
TEN
THOUSANDS
C ÷ 10
Cn+4
Q0 Q3
MUX MUX
SCANNER
RESET 9
SCANNER 10
CLOCK
R
SCANNER
13
CARRY OUT
17
Q3
18
Q2
19
Q1
BCD
OUT
20
Q0
NOTE:
= 3–STATE
OUTPUT BUFFER
7
DS1
8 14 16
DS2 DS3
DS4
DIGIT SELECT
11
DS5
15 3–STATE DIGIT
CONTROL
3–STATE BCD
21 CONTROL
3–State Control
Out
0 Q or DS
1 High Impedance
REV 3
1/94
©MMOotoTrOolaR, IOncL. A199C5MOS LOGIC DATA
DataSheet4 U .com
MC14534B
1
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COUNTER TIMING DIAGRAM
1 2 3 4 5 6 7 8 9 10 102 103
CLOCK A
UNITS Q0
UNITS Q1
UNITS Q2
UNITS Q3
UNITS Cn + 4
TENS Q0
TENS Q3
TENS Cn + 4
HUNDREDS Q0
HUNDREDS Q3
HUNDREDS Cn + 4
THOUSANDS Q0
THOUSANDS Q3
THOUSANDS Cn + 4
TEN THOUSANDS Q0
TEN THOUSANDS Q3
CARRY OUT
MASTER RESET
104 105 106
Mode A
0
0
1
1
Mode B
0
1
1
0
MODE CONTROL TRUTH TABLE
First Stage Output
Carry to Second Stage
Application
Normal Count and Display At 9 to 0 transition of first stage
5–digit Counter
Inhibited
Input Clock
Test Mode: Clock directly into stages 1, 2, and 4.
Inhibited
At 4 to 5 transition of first stage 4–digit counter with ÷ 10 and roundoff at front end.
Counts 3, 4, 5, 6, 7 = 5
Counts 8, 9, 0, 1, 2 = 0
At 7 to 8 transition of first stage
4–digit counter with 1/2 pence capability.
MOTOROLA CMOS LOGIC DATA
DataSheet4 U .com
MC14534B
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet MC14534B.PDF ] | |
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