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PDF MT28F016S5 Data sheet ( Hoja de datos )
| Número de pieza | MT28F016S5 | |
| Descripción | 2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
FLASH MEMORY
MT28F016S5
5V Only, Dual Supply (Smart 5)
FEATURES
• Thirty-two 64KB erase blocks
• Deep Power-Down Mode:
PIN ASSIGNMENT (Top View)
10µA MAX
• Smart 5 technology:
40-Pin TSOP Type I
5V ±10% VCC
5V ±10% VPP application/production
programming
12V VPP tolerant compatibility production
A19
A18
programming
• Address access time: 90ns
• Industry-standard pinouts
A17
A16
A15
A14
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
• Two-cycle WRITE/ERASE sequence
A13
A12
CE#
VCC
VPP
OPTIONS
MARKING
RP#
A11
• Timing
90ns access
-9
DataSheet4U.AcA1o90m
A8
A7
• Package
Plastic 40-pin TSOP Type 1 (10mm x 20mm) VG
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A20
39 NC
38 WE#
37 OE#
36 RY/BY#
35 DQ7
34 DQ6
33 DQ5
32 DQ4
31 VCC
30 VSS
29 VSS
28 DQ3
27 DQ2
26 DQ1
25 DQ0
24 A0
23 A1
22 A2
21 A3
DataShee
Part Number Example:
MT28F016S5VG-9
GENERAL DESCRIPTION
The MT28F016S5 is a nonvolatile, electrically block-
erasable (flash), programmable, read-only memory con-
taining 2,097,152 bytes (8 bits). Writing or erasing the
device is done with a 5V VPP voltage, while all opera-
tions are performed with a 5V VCC. Due to process
technology advances, 5V VPP is optimal for application
and production programming. For backward compat-
ibility with SmartVoltage technology, 12V VPP is sup-
ported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours. The device
is fabricated with Micron’s advanced CMOS floating-
gate process.
DataSheet4U.com
The MT28F016S5 is organized into 32 separately
erasable blocks. ERASEs may be interrupted to allow
other operations with the ERASE SUSPEND command.
After the ERASE SUSPEND command is issued, READ
operations may be executed.
Operations are executed with commands from an
industry-standard command set. In addition to status
register polling, the MT28F016S5 provides a ready/
busy# (RY/BY#) output to indicate WRITE and ERASE
completion.
Please refer to Micron’s Web site (www.micron.com/
flash/htmls/datasheets.html) for the latest data sheet.
2 Meg x 8 Smart 5 Even-Sectored Flash Memory
F42.p65 – Rev. 1/00
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
DataSheet4 U .com
1 page  
www.DataSheet4U.com
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F016S5 flash memory incorporates a num-
INTERNAL STATE MACHINE (ISM)
ber of features that make it ideally suited for system
BLOCK ERASE and WRITE timing are simplified
firmware or data storage. The memory array is seg-
with an ISM that controls all erase and write algorithms
mented into individual erase blocks. Each block may be
in the memory array. The ISM ensures protection against
erased without affecting data stored in other blocks.
over-erasure and optimizes write margin to each cell.
These memory blocks are read, written and erased by
During WRITE operations, the ISM automatically
issuing commands to the command execution logic
increments and monitors WRITE attempts, verifies write
(CEL). The CEL controls the operation of the internal
margin on each memory cell and updates the ISM status
state machine (ISM), which completely controls all
register. When a BLOCK ERASE is performed, the ISM
WRITE, BLOCK ERASE and VERIFY operations. The ISM
automatically overwrites the entire addressed block
protects each memory location from over-erasure and
(eliminates overerasure), increments and monitors
optimizes each memory location for maximum data
ERASE attempts, and sets bits in the ISM status register.
retention. In addition, the ISM greatly simplifies the
control necessary for writing the device in-system or in
ISM STATUS REGISTER
an external programmer.
The ISM status register allows an external processor
The Functional Description provides detailed infor-
to monitor the status of the ISM during WRITE and
mation on the operation of the MT28F016S5 and is
ERASE operations. Two bits of the 8-bit status register
organized into these sections:
are set and cleared entirely by the ISM. These two bits
indicate whether the ISM is busy with an ERASE or
• Overview
WRITE task and when an ERASE has been suspended.
• Memory Architecture
Additional error information is set in three other bits:
et4U.com
• Output (READ) Operations
• Input Operations
VPP status, erase status and write status. These three bits
must be cleared by the host system.
DataShee
• Command Set
• ISM Status Register
DataSheet4UR.EcAomDY/BUSY# (RY/BY#) OUTPUT
• Device Configuration Registers
In addition to status register polling, the MT28F016S5
• Command Execution
provides an asynchronous RY/BY# output to indicate
• Error Handling
the status of the ISM. RY/BY# is VOH when the state
• WRITE/ERASE Cycle Endurance
machine is inactive and VOL during a WRITE or ERASE
• Power Usage
operation. This output is always active.
• Power-Up
COMMAND EXECUTION LOGIC (CEL)
OVERVIEW
SMART 5 TECHNOLOGY
Smart 5 technology allows maximum flexibility for
in-system READ, WRITE and ERASE operations. For 5V-
only systems, WRITE and ERASE operations may be
executed with a VPP voltage of 5V. Due to process
technology advances, 5V VPP is optimal for application
and production programming. For backward compat-
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, device
configuration or status register). Commands may be
issued to the CEL while the ISM is active. However,
there are restrictions on what commands are allowed in
this condition. See the Command Execution section for
more detail.
ibility with SmartVoltage technology, 12V VPP is sup-
ported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours. However,
no performance increase is realized. For any operation,
VCC is at 5V.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F016S5 features a very low current, deep power-
down mode. To enter this mode, the RP# pin is taken to
VSS ±0.2V. In this mode, the current draw is a maximum
THIRTY-TWO INDEPENDENTLY ERASABLE
MEMORY BLOCKS
of 10µA. Entering deep power-down also clears the
status register and sets the ISM to the read array mode.
The MT28F016S5 is organized into 32 indepen-
dently erasable memory blocks that allow portions of
the memory to be erased without affecting the rest of
the memory data.
DataSheet4U.com
2 Meg x 8 Smart 5 Even-Sectored Flash Memory
F42.p65 – Rev. 1/00
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
DataSheet4 U .com
5 Page 
www.DataSheet4U.com
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
ERASE SEQUENCE
Executing an ERASE sequence will set all bits within
ported for a maximum of 100 cycles and may be
a block to logic 1. The command sequence necessary to
connected for up to 100 cumulative hours. Operation
execute an ERASE is similar to that of a WRITE. To
outside these limits may reduce the number of WRITE
provide added security against accidental block era-
and ERASE cycles that can be performed on the device.
sure, two consecutive command cycles are required to
initiate an ERASE of a block. In the first cycle, addresses
POWER USAGE
are “Don’t Care,” and ERASE SETUP (20H) is given. In
the second cycle, VPP is brought to VPPH, an address
within the block to be erased is issued, and ERASE
CONFIRM (D0H) is given. If a command other than
ERASE CONFIRM is given, the write and erase status bits
(SR4 and SR5) will be set, and the device will be in the
read status mode.
After the ERASE CONFIRM (D0H) is issued, the ISM
will start the ERASE of the addressed block. Any READ
operation will output the status register contents on
DQ0-DQ7. VPP must be held at VPPH until the ERASE is
The MT28F016S5 offers several power-saving fea-
tures that may be utilized in the array read mode to
conserve power. Deep power-down mode is enabled by
bringing RP# to VSS ±0.2V. Current draw (ICC) in this
mode is a maximum of 10µA. When CE# is HIGH, the
device will enter standby mode. In this mode, maxi-
mum ICC current is 100µA. If CE# is brought HIGH
during a WRITE or ERASE, the ISM will continue to
operate, and the device will consume the respective
active power until the WRITE or ERASE is completed.
completed (SR7 = 1 and RY/BY# = VOH). Once the ERASE
is completed, the device will be in the status register
read mode until another command is issued.
POWER-UP
The likelihood of unwanted WRITE or ERASE opera-
tions is minimized since two consecutive cycles are
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location not within the block being erased may be read.
If ERASE RESUME is issued before SR6 has been set, the
device will immediately proceed with the ERASE in
progress. During an ERASE SUSPEND, VPP and RP# must
remain at the same levels used for the ERASE.
ERROR HANDLING
After the ISM status bit (SR7) has been set, VPP (SR3),
write (SR4) and erase (SR5) status bits may be checked.
If one or a combination of these four bits has been set,
an error has occurred. The ISM cannot reset these four
RP#
VCC
(5V)
,,,,,,Address
Note 1
tAA
VALID
,,
bits. To clear these bits, CLEAR STATUS REGISTER
(50H) must be given. Table 6 lists the combination of
errors.
WRITE/ERASE CYCLE ENDURANCE
The MT28F016S5 is designed and fabricated to meet
advanced firmware and data storage requirements. To
Data
NOTE:
VALID
,,tRWH
UNDEFINED
1. VCC must be within the valid operating range before RP#
goes HIGH.
ensure this level of reliability, VPP must be at 5V ±10%
during WRITE or ERASE cycles. For SmartVoltage-
Figure 2
compatible production programming, 12V VPP is sup-
Power-Up/Reset Timing Diagram
DataSheet4U.com
2 Meg x 8 Smart 5 Even-Sectored Flash Memory
F42.p65 – Rev. 1/00
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
DataSheet4 U .com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MT28F016S5.PDF ] | |
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