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PDF TMP96C141AF Data sheet ( Hoja de datos )
| Número de pieza | TMP96C141AF | |
| Descripción | CMOS 16-Bit Microcontroller | |
| Fabricantes | Toshiba | |
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TOSHIBA
TLCS-900 Series
TMP96C141AF
CMOS 16-bit Microcontroller
TMP96C141AF
1. Outline and Device Characteristics
The TMP96C141AF is high-speed advanced 16-bit microcon-
troller developed for controlling medium to large-scale equip-
ment.
The TMP96C141AF is housed in an 80-pin flat package.
Device characteristics are as follows:
(1) Original 16-bit CPU
• TLCS-90 instruction mnemonic upward compatible.
• 16M-byte linear address space
• General-purpose registers and register bank system
• 16-bit multiplication/division and bit transfer/arithmetic
instructions
• High-speed micro DMA
- 4 channels (1.6µs/2 bytes @ 20MHz)
(2) Minimum instruction execution time
- 200ns @ 20MHz
(3) Internal RAM: 1K byte
Internal ROM: None
(4) External memory expansion
• Can be expanded up to 16M bytes (for both programs and
data).
• Can mix 8- and 16-bit external data buses.
…Dynamic data bus sizing
(5) 8-bit timers: 2 channels
(6) 8-bit PWM timers: 2 channels
(7) 16-bit timers: 2 channels
(8) Pattern generators: 4 bits, 2 channels
(9) Serial interface: 2 channels
(10) 10-bit A/D converter: 4 channels
(11) Watchdog timer
(12) Chip select/wait controller: 3 blocks
(13) Interrupt functions
• 3 CPU interrupts… …SWI instruction, privileged violation,
and Illegal instruction
• 14 internal interrupts 7-level priority can be set.
• 6 external interrupts
(14) I/O ports
(15) Standby function : 3 halt modes (RUN, IDLE, STOP)
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The information contained here is subject to change without notice.
The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic
equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equip-
ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types
of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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TMP96C141AF
Pin Name
P41
CS1
CAS1
P42
CS2
CAS2
P50 ~ P53
AN0 ~ AN3
VREF
AGND
P60 ~ P63
PG00 ~ PG03
P64 ~ P67
PG10 ~ PG13
P70
T10
P71
T01
P72
T02
P73
T03
P80
TI4
INT4
P81
TI5
INT5
P82
TO4
P83
TO5
Number
of Pins
1
1
4
1
1
4
4
1
1
1
1
1
1
1
1
I/O Functions
I/O
Output
Output
Port 41: I/O port (with pull-up resistor)
Chip select 1: Outputs 0 if address is within specified address area.
Column address strobe 1: Outputs CAS strobe for DRAM if address is within specified address area.
I/O
Output
Output
Port 42: I/O port (with pull-up resistor)
Chip select 2: Outputs 0 if address is within specified address area.
Column address strobe 2: Outputs CAS strobe for DRAM if address is within specified address area.
Input Port 5: Input port
Input Analog input: Input to A/D converter
Input Pin for reference voltage input to A/D converter
Input Ground pin for A/D converter
I/O
Output
Ports 60 - 63: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 00 - 03
I/O
Output
Ports 64 - 67: I/O ports that allow selection of I/O on a bit basis (with pull-up resistor)
Pattern generator ports: 10 - 13
I/O Port 70: I/O port (with pull-up resistor)
Input Timer input 0: Timer 0 input
I/O
Output
Port 71: I/O port (with pull-up resistor)
Timer output 1: Timer 0 or 1 output
I/O
Output
Port 72: I/O port (with pull-up resistor)
PWM output 2: 8-bit PWM timer 2 output
I/O Port 73: I/O port (with pull-up resistor)
Output
PWM output 3: 8-bit PWM timer 3 output
www.DataSheet4U.comI/O Port 80: I/O port (with pull-up resistor)
Input Timer input 4: Timer 4 count/capture trigger signal input
Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling edge
I/O Port 81: I/O port (with pull-up resistor)
Input Timer input 5: Timer 4 count/capture trigger signal input
Input Interrupt request pin 5: Interrupt request pin with rising edge
I/O
Output
Port 82: I/O port (with pull-up resistor)
Timer output 4: Timer 4 output pin
I/O
Output
Port 83: I/O port (with pull-up resistor)
Timer output 5: Timer 4 output pin
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TMP96C141AF
3.3.1 General-Purpose Interrupt Processing
When accepting an interrupt, the CPU operates as follows:
(1) The CPU reads the interrupt vector from the interrupt
controller. When more than one interrupt with the same
level is generated simultaneously, the interrupt controller
generates interrupt vectors in accordance with the
default priority (which is fixed as follows: the smaller the
vector value, the higher the priority), then clears the inter-
rupt request.
(2) The CPU pushes the program counter and the status
register to the system stack area (area indicated by the
system mode stack pointer).
(3) The CPU sets a value in the CPU interrupt mask register
<IFF2 to 0> that is higher by 1 than the value of the
accepted interrupt level. However, if the value is 7, 7 is
set without an increment.
(4) The CPU sets the <SYSM> flag of the status register to 1
and enters the system mode.
(5) The CPU jumps to address 8000H + interrupt vector,
then starts the interrupt processing routine.
Bus Width of Stack
Area
8 bit
16 bit
Interrupt Processing State Number
MAX mode
Min mode
23 19
17 15
To return to the main routine after completion of the inter-
rupt processing, the RETI instruction is usually used. Executing
this instruction restores the contents of the program counter
and the status registers.
Though acceptance of non-maskable interrupts cannot
be disabled by program, acceptance of maskable interrupts
can. A priority can be set for each source of maskable inter-
rupts. The CPU accepts an interrupt request with a priority
higher than the value in the CPU mask register <IFF2 to 0>.
The CPU mask register <IFF2 to 0> is set to a value higher by
1 than the priority of the accepted interrupt. Thus, if an inter-
rupt with a level higher than the interrupt being processed is
generated, the CPU accepts the interrupt with the higher level,
causing interrupt processing to nest. The CPU does not
accept an interrupt request of the same level as that of the
interrupt being processed.
Resetting initializes the CPU mask registers <IFF2 to 0>
to 7; therefore, maskable interrupts are disabled.
The addresses 008000H to 0081FFH (512 bytes) of the
TLCS-900 are assigned for interrupt processing entry area.
In minimum mode, all the above processing is completed
www.DataSheet4U.comin 15 states (1.5µs @ 20MHz). In maximum mode, it is com-
pleted in 17 states.
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