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PDF MX29LV400CT Data sheet ( Hoja de datos )
| Número de pieza | MX29LV400CT | |
| Descripción | (MX29LV400CB/T) 4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX29LV400C T/B
FEATURES
4M-BIT [512K x 8 / 256K x 16] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
• Extended single - supply voltage range 2.7V to 3.6V
• 524,288 x 8/262,144 x 16 switchable
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fully compatible with MX29LV400T/B device
• Fast access time: 55R/70/90ns
• Low power consumption
- 30mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte/word Programming (9us/11us typical)
- Sector Erase (Sector structure 16K-Byte x 1,
8K-Byte x 2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase
• Status Reply
- Data# Polling & Toggle bit for detection of program
and erase operation completion
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Temporary sector unprotect allows code changes in
previously locked sectors
• CFI (Common Flash Interface) compliant
- Flash device parameters stored on the device and
provide the host system to access
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Package type:
- 44-pin SOP
- 48-pin TSOP
- 48-ball CSP (6 x 8mm)
- 48-ball CSP (4 x 6mm)
- All Pb-free devices are RoHS Compliant
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX29LV400C T/B is a 4-mega bit Flash memory
organized as 512K bytes of 8 bits or 256K words of 16
bits. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX29LV400C T/B is packaged in 44-pin
mSOP, 48-pin TSOP and 48-ball CSP. It is designed to be
oreprogrammed and erased in system or in standard
.cEPROM programmers.
UThe standard MX29LV400C T/B offers access time as
t4fast as 55ns, allowing operation of high-speed micropro-
ecessors without wait states. To eliminate bus conten-
etion, the MX29LV400C T/B has separate chip enable
h(CE#) and output enable (OE#) controls.
SMXIC's Flash memories augment EPROM functionality
tawith in-circuit electrical erasure and programming. The
aMX29LV400C T/B uses a command register to manage
.Dthis functionality. The command register allows for 100%
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1
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV400C T/B uses a 2.7V~3.6V VCC
supply to perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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BLOCK DIAGRAM
MX29LV400C T/B
CE#
OE#
WE#
RESET#
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
A0-A17
ADDRESS
LATCH
AND
BUFFER
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
STATE
REGISTER
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
U.comQ0-Q15/A-1
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PROGRAM
DATA LATCH
I/O BUFFER
5
COMMAND
DATA LATCH
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MX29LV400C T/B
gram or erase operation is completed within a time of
tREADY (not during Embedded Algorithms).The system
can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 24 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the read/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data. The de-
vice remains enabled for reads until the command regis-
ter contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high voltage
onto address lines is not generally desired system de-
sign practice.
sector erase command 30H.
The Automatic Chip Erase does not require the device to
be entirely pre-programmed prior to executing the Auto-
matic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero pat-
tern, a self-timed chip erase and verify begin. The erase
and verify operations are completed when the data on
Q7 is "1" at which time the device returns to the Read
mode. The system is not required to provide any control
or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 7), indicating the erase operation ex-
ceed internal timing limit.
The automatic erase begins on the rising edge of the last
WE# or CE# pulse, whichever happens first in the com-
mand sequence and terminates when the data on Q7 is
"1" at which time the device returns to the Read mode,
or the data on Q6 stops toggling for two consecutive read
cycles at which time the device returns to the Read mode.
The MX29LV400C T/B contains a Silicon-ID-Read op-
eration to supple traditional PROM programming meth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
mA1=VIL, A0=VIL retrieves the manufacturer code of C2H/
o00C2H. A read cycle with A1=VIL, A0=VIH returns the
.cdevice code of B9H/22B9H for MX29LV400CT, BAH/
22BAH for MX29LV400CB.
t4USET-UP AUTOMATIC CHIP/SECTOR ERASE COM-
eMANDS
heChip erase is a six-bus cycle operation. There are two
S"unlock" write cycles. These are followed by writing the
ta"set-up" command 80H. Two more "unlock" write cycles
aare then followed by the chip erase command 10H or
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REV. 1.5, APR. 24, 2006
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX29LV400CT.PDF ] | |
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