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PDF MIPS324KP Data sheet ( Hoja de datos )
| Número de pieza | MIPS324KP | |
| Descripción | Processor Core | |
| Fabricantes | MIPS Technologies | |
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MIPS32 4Kp™ Processor Core Datasheet
March 6, 2002
The MIPS32™ 4Kp™ core from MIPS® Technologies is a member of the MIPS32 4K™ processor core family. It is a
high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is
designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate
their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and
can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user
products. The 4Kp core is ideally positioned to support new products for emerging segments of the digital consumer,
network, systems, and information management markets, enabling new tailored solutions for embedded applications.
The 4Kp core implements the MIPS32 Architecture and contains all MIPS II™ instructions; special multiply-accumulate
(MAC), conditional move, prefetch, wait, and leading zero/one detect instructions; and the 32-bit privileged resource
architecture. The Memory Management Unit consists of a simple, fixed Block Address Translation (BAT) mechanism for
applications that do not require the full capabilities of a Translation Lookaside Buffer based MMU.
Instruction and data caches are fully configurable from 0 - 16 Kbytes in size. In addition, each cache can be organized as
direct-mapped or 2-way, 3-way, or 4-way set associative. Load and fetch cache misses only block until the critical word
becomes available. The pipeline resumes execution while the remaining words are being written to the cache. Both caches
are virtually indexed and physically tagged to allow them to be accessed in the same clock that the address is translated.
An optional Enhanced JTAG (EJTAG) block allows for single-stepping of the processor as well as instruction and data
virtual address breakpoints.
Figure 1 shows a block diagram of the 4Kp core. The core is divided into required and optional blocks as shown.
Mul/Div Unit
Processor Core
Instruction
Cache
EJTAG
Execution
Core
MMU
Cache
Control
System
Coprocessor
BAT
Data
Cache
Power
Mgmt.
Fixed/Required
Optional
Figure 1 4Kp Core Block Diagram
Features
• 32-bit Address and Data Paths
MIPS32 4Kp™ Processor Core Datasheet, Revision 01.07
Copyright © 1999-2002 MIPS Technologies Inc. All right reserved.
www.DataSheet4U.com
1 page  
Table 2 Coprocessor 0 Registers in Numerical Order
Register
Number
4
5
6
Register
Name
Context2
PageMask1
Wired1
Function
Pointer to page table entry in
memory.
Reserved in the 4Kp core.
Reserved in the 4Kp core.
7 Reserved Reserved.
8 BadVAddr2 Reports the address for the most
recent address-related exception.
9 Count2
Processor cycle count.
10 EntryHi1 Reserved in the 4Kp core.
11 Compare2 Timer interrupt control.
12 Status2
Processor status and control.
13 Cause2
Cause of last general exception.
14 EPC2
Program counter at last exception.
15 PRId
Processor identification and
revision.
16 Config
Configuration register.
16 Config1 Configuration register 1.
17 LLAddr Load linked address.
18 WatchLo2 Low-order watchpoint address.
19 WatchHi2 High-order watchpoint address.
20 - 22
23
Reserved
Debug3
24 DEPC3
Reserved.
Debug control and exception
status.
Program counter at last debug
exception.
25 - 27 Reserved Reserved.
28 TagLo/
DataLo
Low-order portion of cache tag
interface.
29 Reserved Reserved.
30 ErrorEPC2 Program counter at last error.
31 DeSave3 Debug handler scratchpad register.
1. Registers used in memory management.
2. Registers used in exception processing.
3. Registers used during debug.
Coprocessor 0 also contains the logic for identifying and
managing exceptions. Exceptions can be caused by a
variety of sources, including boundary cases in data,
external events, or program errors. Table 3 shows the
exception types in order of priority.
Table 3 4Kp Core Exception Types
Exception
Reset
Soft Reset
DSS
DINT
NMI
Machine Check
Interrupt
Deferred Watch
DIB
WATCH
AdEL
TLBL
IBE
DBp
Sys
Bp
RI
CpU
Ov
Tr
Description
Assertion of SI_ColdReset signal.
Assertion of SI_Reset signal.
EJTAG Debug Single Step.
EJTAG Debug Interrupt. Caused by the
assertion of the external EJ_DINT
input, or by setting the EjtagBrk bit in
the ECR register.
Assertion of EB_NMI signal.
TLB write that conflicts with an
existing entry.
Assertion of unmasked hardware or
software interrupt signal.
Deferred Watch (unmasked by K|DM-
>!(K|DM) transition).
EJTAG debug hardware instruction
break matched.
A reference to an address in one of the
watch registers (fetch).
Fetch address alignment error.
Fetch reference to protected address.
Fetch TLB miss.
Instruction fetch bus error.
EJTAG Breakpoint (execution of
SDBBP instruction).
Execution of SYSCALL instruction.
Execution of BREAK instruction.
Execution of a Reserved Instruction.
Execution of a coprocessor instruction
for a coprocessor that is not enabled.
Execution of an arithmetic instruction
that overflowed.
Execution of a trap (when trap
condition is true).
MIPS32 4Kp™ Processor Core Datasheet, Revision 01.07
Copyright © 1999-2002 MIPS Technologies Inc. All right reserved.
5
5 Page 
• Uncached: Addresses in a memory area indicated as
uncached are not read from the cache. Stores to such
addresses are written directly to main memory, without
changing cache contents.
• Write-through: Loads and instruction fetches first
search the cache, reading main memory only if the
desired data does not reside in the cache. On data store
operations, the cache is first searched to see if the
target address is cache resident. If it is resident, the
cache contents are updated, and main memory is also
written. If the cache look-up misses, only main
memory is written.
Scratchpad RAM
The 4Kp core also supports replacing up to one way of each
cache with a scratchpad RAM. The scratchpad RAM is
user-defined and can consist of a variety of devices. The
main requirement is that it must be accessible with timing
similar to a regular cache RAM. This means that an index
will be driven one cycle, a tag will be driven the following
clock, and the scratchpad must return a hit signal and the
data in the second clock. The scratchpad can thus easily
contain a large RAM/ROM or memory-mapped registers.
The core’s interface to a scratchpad RAM is slightly
different than to a regular cache RAM. Additional index
bits allow access to a larger array, 1MB of scratchpad RAM
versus 4KB for a cache way. The core does not
automatically refill the scratchpad way and will not select
it for replacement on cache misses. Additionally, stores that
hit in the scratchpad will not generate write-throughs to
main memory.
EJTAG Debug Support
The 4Kp core provides for an optional Enhanced JTAG
(EJTAG) interface for use in the software debug of
application and kernel code. In addition to standard user
mode and kernel modes of operation, the 4Kp core
provides a Debug mode that is entered after a debug
exception (derived from a hardware breakpoint, single-step
exception, etc.) is taken and continues until a debug
exception return (DERET) instruction is executed. During
this time, the processor executes the debug exception
handler routine.
The EJTAG interface operates through the Test Access Port
(TAP), a serial communication port used for transferring
test data in and out of the 4Kp core. In addition to the
standard JTAG instructions, special instructions defined in
the EJTAG specification define what registers are selected
and how they are used.
Debug Registers
Three debug registers (DEBUG, DEPC, and DESAVE)
have been added to the MIPS Coprocessor 0 (CP0) register
set. The DEBUG register shows the cause of the debug
exception and is used for the setting up of single-step
operations. The DEPC, or Debug Exception Program
Counter, register holds the address on which the debug
exception was taken. This is used to resume program
execution after the debug operation finishes. Finally, the
DESAVE, or Debug Exception Save, register enables the
saving of general-purpose registers used during execution
of the debug exception handler.
To exit debug mode, a Debug Exception Return (DERET)
instruction is executed. When this instruction is executed,
the system exits debug mode, allowing normal execution of
application and system code to resume.
EJTAG Hardware Breakpoints
There are several types of simple hardware breakpoints
defined in the EJTAG specification. These stop the normal
operation of the CPU and force the system into debug
mode. There are two types of simple hardware breakpoints
implemented in the 4Kp core: Instruction breakpoints and
Data breakpoints.
The 4Kp core can be configured with the following
breakpoint options:
• No data or instruction breakpoints
• One data and two instruction breakpoints
• Two data and four instruction breakpoints
Instruction breaks occur on instruction fetch operations,
and the break is set on the virtual address on the bus
between the CPU and the instruction cache. Instruction
breaks can also be made on the ASID value used by the
MMU. Finally, a mask can be applied to the virtual address
to set breakpoints on a range of instructions.
Refer to the section called "4Kp Core Signal Descriptions"
on page 16 for a list of signals EJTAG interface signals.
Data breakpoints occur on load/store transactions.
Breakpoints are set on virtual address and ASID values,
similar to the Instruction breakpoint. Data breakpoints can
be set on a load, a store, or both. Data breakpoints can also
MIPS32 4Kp™ Processor Core Datasheet, Revision 01.07
Copyright © 1999-2002 MIPS Technologies Inc. All right reserved.
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