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PDF MX26LV004B Data sheet ( Hoja de datos )
| Número de pieza | MX26LV004B | |
| Descripción | (MX26LV004T/B) 4M-Bit CMOS Single Voltage Flash Memory | |
| Fabricantes | Macronix | |
| Logotipo |  |
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ADVANCED INFORMATION
MX26LV004T/B
Macronix NBitTM Memory Family
4M-BIT [512K x 8] CMOS SINGLE VOLTAGE
3V ONLY HIGH SPEED eLiteFlashTM MEMORY
FEATURES
• Extended single - supply voltage range 3.0V to 3.6V
• 524,288 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 55/70ns
• Low power consumption
- 30mA maximum active current
- 30uA typical standby current
• Command register architecture
- Byte Programming (55us typical)
- Sector Erase (Sector structure 16K-Byte x1,
8K-Byte x2, 32K-Byte x1, and 64K-Byte x7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Status Reply
- Data polling & Toggle bit for detection of program and
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• 2,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- 40-pin TSOP
- 32-pin PLCC
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX26LV004T/B is a 4-mega bit Flash memory orga-
nized as 512K bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX26LV004T/B is
packaged in 40-pin TSOP. It is designed to be repro-
grammed and erased in system or in standard EPROM
programmers.
The standard MX26LV004T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX26LV004T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX26LV004T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 2,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX26LV004T/B uses a 3.0V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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MX26LV004T/B
AUTOMATIC PROGRAMMING
The MX26LV004T/B is byte programmable using the Au-
tomatic Programming algorithm. The Automatic Pro-
gramming algorithm makes the external system do not
need to have time out sequence nor to verify the data
programmed.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation. Refer to write operation status, table 7, for more
information on these status bits.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
The Automatic Erase algorithm automatically programs
the entire array prior to electrical erase. The timing and
verification of electrical erase are controlled internally
within the device.
the device automatically times the erase pulse width,
provides the erase verification, and counts the number of
sequences. A status bit toggling between consecutive
read cycles provides feedback to the user as to the sta-
tus of the erasing operation.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of WE or CE, whichever hap-
pens first.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness.The MX26LV004T/B elec-
trically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command regis-
ter to respond to its full command set.
AUTOMATIC SECTOR ERASE
The MX26LV004T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. The Automatic Sector
Erase algorithm automatically programs the specified
sector(s) prior to electrical erase. The timing and verifi-
cation of electrical erase are controlled internally within
the device. An erase operation can erase one sector,
multiple sectors, or the entire device.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
AUTOMATIC SELECT
The auto select mode provides manufacturer and de-
vice identification, through identifier codes output on
Q7~Q0. This mode is mainly adapted for programming
equipment on the device to be programmed with its pro-
gramming algorithm.When programming by high voltage
method, automatic select mode requires VID (11V to 12V)
on address pin A9 and other address pin A6, A1 and A0
as referring to Table 3. In addition, to access the auto-
matic select codes in-system, the host can issue the
automatic select command through the command regis-
ter without requiring VID, as shown in table 4.
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MX26LV004T/B
TABLE 6. SILICON ID CODE
Pins
Manufacture code
Device code
for MX26LV004T
Device code
for MX26LV004B
A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
VIL VIL 1 1 0 0 0 0 1 0 C2H
VIH VIL 1 0 1 1 0 1 0 1 B5H
VIH VIL 1 0 1 1 0 1 1 0 B6H
READING ARRAY DATA
The device is automatically set to reading array data
after device power-up. No commands are required to re-
trieve data. The device is also ready to read array data
after completing an Automatic Program or Automatic
Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data. Af-
ter completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See erase Suspend/Erase
Resume Commands” for more infor-mation on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if Q5 goes high, or
while in the autoselect mode. See the "Reset Command"
section, next.
RESET COMMAND
Writing the reset command to the device resets the
device to reading array data. Address bits are don't care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-fore
programming begins. This resets the device to reading
array data (also applies to programming in Erase Suspend
mode). Once programming begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in an SILICON ID READ command
sequence. Once in the SILICON ID READ mode, the
reset command must be written to return to reading array
data (also applies to SILICON ID READ during Erase
Suspend).
If Q5 goes high during a program or erase operation,
writing the reset command returns the device to read-ing
array data (also applies during Erase Suspend).
P/N:PM1099
REV. 0.02, JUL. 12, 2004
11
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