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PDF SST34HF162x Data sheet ( Hoja de datos )
| Número de pieza | SST34HF162x | |
| Descripción | (SST34HF162x / SST34HF164x) 16M-bit Concurrent SuperFlash + SRAM | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
SST31VF201 / 401 / 8012Mb/4Mb/8Mb Flash (x16) + 1MbSRAM (x16) ComboMemories
FEATURES:
Preliminary Specifications
• Flash Organization: 1M x16
• Dual-Bank Architecture for Concurrent
Read/Write Operation
– SST34HF16x1: 12Mbit + 4 Mbit
– SST34HF16x2: 4 Mbit + 12 Mbit
• SRAM Organization:
– 2 Mbit: 256K x8 or 128K x16
– 4 Mbit: 512K x8 or 256K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 25 mA (typical)
– Standby Current: 20 µA (typical)
– Auto Low Power Mode: 20 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Sector-Erase Capability
– Uniform 1 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Read Access Time
– Flash: 70 and 90 ns
– SRAM: 70 and 90 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Conforms to Common Flash Memory Interface
(CFI)
• Packages Available
– 56-ball LFBGA (8mm x 10mm)
– 48-ball LFBGA (6mm x 8mm)
PRODUCT DESCRIPTION
The SST34HF162x/164x ComboMemory devices inte-
grate a 1M x16 CMOS flash memory bank with a 256K x8/
128K x16 or 512K x8/ 256K x16 CMOS SRAM memory
bank in a Multi-Chip Package (MCP). These devices are
fabricated using SST’s proprietary, high-performance
CMOS SuperFlash technology incorporating the split-gate
cell design and thick oxide tunneling injector to attain better
reliability and manufacturability compared with alternate
approaches. The SST34HF162x/164x devices are ideal for
applications such as cellular phones, GPSs, PDAs and
other portable electronic devices in a low power and small
form factor system.
The SST34HF162x/164x features dual flash memory bank
architecture allowing for concurrent operations between the
two flash memory banks and the SRAM. The devices can
read data from either bank while an Erase or Program
operation is in progress in the opposite bank. The two flash
memory banks are partitioned into 4 Mbits and 12 Mbits
with top or bottom sector protection options for storing boot
code, program code, configuration/parameter data and
user data.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF162x/164x devices offer a
guaranteed endurance of 10,000 cycles. Data retention is
rated at greater than 100 years. With high performance
Word-Program, the flash memory banks provide a typical
Word-Program time of 14 µsec. The entire flash memory
bank can be erased and programmed word-by-word in typ-
ically 8 seconds for the SST34HF162x/164x, when using
interface features such as Toggle Bit or Data# Polling to
indicate the completion of Program operation. To protect
against inadvertent flash write, the SST34HF162x/164x
devices contain on-chip hardware and software data pro-
tection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
©2001 Silicon Storage Technology, Inc.
S71172-03-000 7/01
523
1
www.DataSheet4U.com
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Concurrent SuperFlash and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
Preliminary Specifications
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 18 for timing waveform and Figure 25 for a
flowchart.
SRAM Operation
With BES1# low, BES2 and BEF# high, the
SST34HF162x operates as 256K x8 or 128K x16 CMOS
SRAM, and the SST34HF164x operates as 512K x8 or
256K x16 CMOS SRAM, with fully static operation requir-
ing no external clocks or timing strobes. The CIOs pin
configures the SRAM for x8 or x16 SRAM operation
modes. The SST34HF162x SRAM is mapped into the
first 256 KByte/128 KWord address space of the device,
and the SST34HF164x SRAM is mapped into the first
512 KByte/256 KWord address space. When BES1#,
BEF# are high and BES2 is low, all memory banks are
deselected and the device enters standby. Read and
Write cycle times are equal. The control signals UBS#
and LBS# provide access to the upper data byte and
lower data byte. See Table 3 for SRAM Read and Write
data byte control modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF162x/164x is
controlled by OE# and BES1#, both have to be low with
WE# and BES2 high for the system to obtain data from the
outputs. BES1# and BES2 are used for SRAM bank selec-
tion. OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing diagram,
Figure 5, for further details.
SRAM Write
The SRAM Write operation of the SST34HF162x/164x is
controlled by WE# and BES1#, both have to be low, BES2
have to be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagram, Figures 6 and 7, for further details.
FUNCTIONAL BLOCK DIAGRAM
AMS - A0
Address
Buffers
RST#
BEF#
WP#
SA
LBS#
UBS#
WE#
OE#
BES1#
BES2
CIOs
RY/BY#
Control
Logic
Address
Buffers
AMS = Most significant address
SuperFlash Memory
(Bank 1)
SuperFlash Memory
(Bank 2)
I/O Buffers
DQ15 - DQ8
DQ7 - DQ0
2 Mbit or 4 Mbit
SRAM
503 ILL B1.1
©2001 Silicon Storage Technology, Inc.
5
S71172-03-000 7/01 523
5 Page 
16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM
SST34HF162x / SST34HF164x
Preliminary Specifications
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
Word-Program
Sector-Erase
Block-Erase
Chip-Erase
Software ID Entry5
CFI Query Entry5
Software ID Exit/
CFI Exit6
Software ID Exit/
CFI Exit6
1st Bus
Write Cycle
Addr1 Data2
5555H AAH
5555H AAH
5555H AAH
5555H AAH
5555H AAH
5555H AAH
XXH F0H
2nd Bus
Write Cycle
Addr1 Data2
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
3rd Bus
Write Cycle
Addr1 Data2
5555H A0H
5555H 80H
5555H 80H
5555H 80H
5555H 90H
5555H 98H
4th Bus
Write Cycle
Addr1 Data2
WA3 Data
5555H AAH
5555H AAH
5555H AAH
5th Bus
Write Cycle
Addr1 Data2
2AAAH
2AAAH
2AAAH
55H
55H
55H
5555H AAH 2AAAH 55H 5555H F0H
1. Address format A14-A0 (Hex),Address A15-A19 can be VIL or VIH, but no other value, for the Command sequence.
2. Data format DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence.
3. WA = Program Word address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX, for Block-Erase; uses A19-A15 address lines
5. The device does not remain in Software Product Identification Mode if powered down.
6. Both Software ID Exit operations are equivalent
6th Bus
Write Cycle
Addr1 Data2
SAX4
BAX4
5555H
30H
50H
10H
T4.3 523
TABLE 5: CFI QUERY IDENTIFICATION STRING1
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
1. Refer to CFI publication 100 for more details.
T5.0 523
©2001 Silicon Storage Technology, Inc.
11
S71172-03-000 7/01 523
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST34HF162x.PDF ] | |
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