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PDF SIS630 Data sheet ( Hoja de datos )
| Número de pieza | SIS630 | |
| Descripción | Single Chipset | |
| Fabricantes | SIS | |
| Logotipo |  |
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SiS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Content
1 SiS630 Overview .....................................................................................................1
1.1 Function Block Reference Table................................................................3
2 Features..................................................................................................................5
3 Pin Assignment......................................................................................................12
3.1 Pin Assignment (Top View).....................................................................12
3.1.1 SiS630 Pin Assignment (Top View-Left Side) ...................................12
3.1.2 SiS630 Pin Assignment (Top View-Right Side).................................13
m3.2 SiS630 Alphabetical Pin List ...................................................................14
3.3 Power Plane..........................................................................................20
o3.4 Muxpin..................................................................................................21
.c4 Pin Description (Preliminary) ..................................................................................23
4.1 Host Bus Interface .................................................................................23
4.2 DRAM Controller....................................................................................27
U4.3 PCI Interface .........................................................................................27
4.4 PCI IDE Interface...................................................................................32
t44.5 VGA Interface........................................................................................33
4.6 Power management Interface.................................................................36
e4.7 SMBus Interface ....................................................................................37
4.8 Keyboard controller Interface..................................................................38
e4.9 LPC Interface ........................................................................................39
4.10 RTC Interface ........................................................................................39
h4.11 AC’ 97 interface......................................................................................40
S4.12 Fast Ethernet and Homenetworking interface ..........................................41
4.13 USB interface ........................................................................................43
ta4.14 Legacy I/o and Miscellaneous Signals.....................................................44
4.15 Power and Ground Signals .....................................................................44
5 Hardware Trap.......................................................................................................46
a6 Function Description ..............................................................................................49
6.1 MA Mapping Table .................................................................................49
.D6.1.1 SDRAM/System Memory................................................................49
6.1.2 SDRAM/FBC .................................................................................50
6.1.3 VCM/System Memory ....................................................................51
w6.1.4 VCM/FBC......................................................................................54
6.2 PSON# and ACPILED Description ..........................................................55
w6.2.1 ACPI.............................................................................................57
w6.3 Power States for SiS630 Signals.............................................................58
6.4 Arbiter Tree ...........................................................................................62
6.5 Nand Tree Test Scheme.........................................................................63
om7 Register Summary / Description – Core Logic..........................................................67
.c7.1 Device 0, Function 0 ( Host-to-PCI Bridge) ..............................................67
7.1.1 Configuration Space Header...........................................................67
t4U7.1.2 Registers for Host & DRAM ............................................................68
7.1.3 Shadow RAM & PCI-Hole Area.......................................................69
www.DataSheePreliminary V.10 Oct.07,1999
i Silicon Integrated Systems Corporation
1 page  
SiS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
Revision History
Date
Rev
Description
Oct.1999
1.0
1.Revisions to Chapter 3 A4, A7,B4, C5, D5 ,M12,M13,M14
Pin List delete "EEDI/F8"
2.Revision to 3.4 Muxpin Ball No.W4
1.Removed GPIO9/PLED1#/OC4# in Chap.4.
2.Revisions to Chapter 4 USB (UV[4:0])
3.Change "PLED0/OC3#/GPIO8" to "PLED0/OC2#/GPIO8" ,
“LDRQ1#/OC2#/GPIO2" to "LDRQ1#/OC3#/GPIO2" and
"ACTIVITY indication" to "LINK/ACTIVITY indication"
4.Revision to 4.5 VGA Interface Name VBA1.
5.Revision to 4.12 PLED#.
6.Revision to 4.15 PHYVDD.
1.Add Arbiter Tree to Chap 6
2.Revisions to Mapping Table.
3.Revisions to 6.3 CPURST# and CKE.
1.Revision7.3.2 Register 08h.
1.Revisions to Chap.8 IDE Register
1.Revisions to 9.9 CNFG04,CNFG3C.
1. Revisions to Chap.10-11_South_Bridge
Add an interrupt pin table.
Change some description of Reg 40h
Remove the description " These registers can be accessed
from PCI bus and ISA bus".
1.Revisions to Chap.11 Register 5F Reg47, Reg48, Reg62
Reg72 , Reg73, Reg6a and Reg76
1.Revisions to Chap 14 (Audio)
Preliminary V.10 Oct.07,1999
v Silicon Integrated Systems Corporation
5 Page 
SiS630 Slot 1/Socket 370 2D/3D Ultra-AGPTM Single Chipset
2 Features
Host Interface Controller
n Supports Intel Pentium II/!!! CPU at 66MHz/100MHz Front Side Bus Frequency
n Synchronous Host/DRAM Clock Scheme
n Asynchronous Host/DRAM Clock Scheme
Integrated DRAM Controller
n 3-DIMM/6-Bank of 3.3V SDRAM
n Supports NEC Virtual Channel Memory (VC-SDRAM) Technology
n Supports Memory Bus up to 133 MHZ
n System Memory Size up to 1.5 GB
n Up to 512MB per Row
n Supports 16Mb, 64Mb, 128Mb, 256Mb, 512Mb SDRAM Technology
n Suspend-to-RAM (STR)
n Relocatable System Management Memory Region
n Programmable Buffer Strength for CS#, DQM[7:0], WE#, RAS#, CAS#, CKE, MA[14:0]
and MD[63:0]
n Shadow RAM Size from 640KB to 1MB in 16KB increments
n Two Programmable PCI Hole Areas
Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
n AGP v2.0 Compliant
n Supports Graphic Window Size from 4MBytes to 256MBytes
n Supports Pipelined Process in CPU-to-Integrated 3D A.G.P. VGA Access
n Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance Integrated A.G.P.
VGA Controller Read/Write Performance
n Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to
Integrated A.G.P. VGA
Meet PC99 Requirements
PCI 2.2 Specification Compliant
High Performance PCI Arbiter
n Supports up to 4 PCI Masters
n Rotating Priority Arbitration Scheme
n Advanced Arbitration Scheme Minimizing Arbitration Overhead.
n Guaranteed Minimum Access Time for CPU And PCI Masters
Integrated Host-To-PCI Bridge
n Zero Wait State Burst Cycles
n CPU-to-PCI Pipeline Access
n 256B to 4KB PCI Burst Length for PCI Masters
n PCI Master Initiated Graphical Texture Write Cycles Re-mapping
Preliminary V.10 Oct.07,1999
5 Silicon Integrated Systems Corporation
11 Page | ||
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| PDF Descargar | [ Datasheet SIS630.PDF ] | |
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