|
|
PDF MPC2004 Data sheet ( Hoja de datos )
| Número de pieza | MPC2004 | |
| Descripción | (MPC2004 / MPC2005) 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MPC2004 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC2004/D
Advance Information
256KB and 512KB BurstRAM™
Secondary Cache Modules for
PowerPC™ PReP/CHRP Platforms
MPC2004
MPC2005
The MPC2004 and MPC2005 are designed to provide burstable, high perfor-
mance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in
conformance with the PowerPC Reference Platform (PReP) and the PowerPC
Common Hardware Reference Platform (CHRP) specifications. The modules
are configured as 32K x 72 and 64K x 72 bits in a 182 (91 x 2) pin DIMM format.
mEach module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and
oa 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and
dirty status bits.
.cBursts can be initiated with the SRAMADS signal. Subsequent burst address-
es are generated internal to the BurstRAM by the SRAMCNTEN signal.
Write cycles are internally self timed and are initiated by the rising edge of the
Uclock (CLKx) inputs. Eight write enables are provided for byte write control.
Presence detect pins are available for auto configuration of the cache control.
t4A serial EEPROM is optional to provide more in–depth description of the
cache module.
The module family pinout will support 5 V and 3.3 V components for a clear path
eto lower voltage and power savings. Both power supplies must be connected.
These cache modules are plug and pin compatible with the MPC2006, a 1MB
esynchronous module also designed for the PReP and CHRP specifications.
hThey are also compatible with the MPC2007 and MPC2009, 256KB and 1MB re-
spectively, asynchronous cache modules.
S• PowerPC–style Burst Counter on Chip
ta• Flow–Through Data I/O
• Module Requires Both 3.3 V and 5 V Power Supplies
a• Multiple Clock Pins for Reduced Loading
.D• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible
• Three State Outputs
w• Byte Write Capability
• Fast Module Clock Rates: 66 MHz
w• Fast SRAM Access Times: 10 ns for Tag RAM Match
m9 ns for Data RAM
w .co• Decoupling Capacitors for Each Fast Static RAM
U• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
t4• 182 Pin Card Edge Module
e• Burndy Connector, Part Number: ELF182JSC–3Z50
SheBurstRAM is a trademark of Motorola.BurstRAM is a trademark of Motorola.
taPowerPC is a trademark of International Business Machines Corp.
aThis document contains information on a new product. Specifications and information herein are subject to change without notice.
w.D5/95
wwM© OMoTtoOroRla,OInLc.A19F95AST SRAM
MPC2004•MPC2005
6–1
1 page  
PIN DESCRIPTIONS
Pin Locations
68, 69, 70, 71, 73, 74, 75,
76, 78, 79, 80, 82, 83, 84,
85, 159, 160, 161, 162,
164, 165, 166, 167, 169,
170, 171, 173, 174, 175
62, 63
153, 154
30, 56, 117, 146, 148
Symbol
A0 – A28
ADDR0A,
ADDR0B
ADDR1A,
ADDR1B
CLK0 – CLK4
4, 5, 6, 7, 10, 11, 12, 14,
16, 17, 19, 20, 22, 24, 25,
26, 27, 95, 96, 97, 98, 101,
102, 103, 105, 107, 108,
110, 111, 113, 115, 119
32, 33, 34, 37, 38, 39, 40,
43, 44, 45, 47, 49, 50, 52,
53, 54, 121, 122, 124, 125,
126, 129, 130, 131, 133,
135, 136, 138, 139, 141,
143, 144
9, 15, 21, 28, 35, 42, 48, 58
3, 94
2
93
64, 65
151
155, 156
59, 60
100, 106, 112, 120, 128,
134, 140, 150
87
88
178
179
89
90
181
180
176
8, 23, 51, 61, 77, 99, 114,
142, 152, 168
DH0 – DH31
DL0 – DL31
DP0 – DP7
PD2, PD3
PD0/IDSCLK
PD1/IDSDATA
SRAMADS0,
SRAMADS1
SRAM ALE
SRAMCNTEN0,
SRAMCNTEN1
SRAMOE0,
SRAMOE1
SRAMWE0 –
SRAMWE7
TAGCLR
TAG MATCH
TAG VALID
TAGWE
TAGOE
DIRTYIN
DIRTYOUT
STANDBY
RESERVED
VCC3
Type
Input
Description
Address Inputs – (MSB:0, LSB:28)
Input Least significant address bit when asynchronous SRAMs are used.
Input Next to least significant address bit when asynchronous SRAMs are used.
Input
I/O
Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for SRAMs.
For 1MB use all the clocks. For 512KB or less us CLK0–CLK2 only.
High Data Bus – (MSB:0, LSB:31)
I/O Low Data Bus – (MSB:0, LSB:31)
I/O
Output
Input
I/O
Input
Data Parity Bus – (MSB:0, LSB:7)
Presence detect bits 2 and 3.
Presence detect bit 0/EEPROM serial clock.
Presence detect bit 1/EEPROM serial data.
SRAM Address Strobe – For 512KB or less us SRAM ADS0 only.
Input
Input
SRAM Address Latch Enable – Use for asynchronous SRAM only.
SRAM Count Enables – For 512KB or less use SRAM CNT EN0 only.
Input SRAM Output Enables – For 512KB or less use SRAM OE0 only.
Input SRAM Write Enables – (MSB:0, LSB:7)
Input
Output
Input
Input
Input
Input
Output
Input
Input
Tag RAM clear.
Tag RAM match indication.
Tag RAM valid bit.
Tag RAM write enable.
Tag RAM output enable.
Dirty input bit.
Dirty output bit.
Standby pin. Reduces standby power consumption.
Reserved pin.
+ 3.3 V power supply.
MOTOROLA FAST SRAM
MPC2004•MPC2005
6–5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MPC2004.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MPC2001 | 256KB Asynchronous Secondary Cache Module for PowerPC | Motorola Semiconductors |
| MPC2002 | (MPC2002 / MPC2003) 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems | Motorola Semiconductors |
| MPC2003 | (MPC2002 / MPC2003) 256KB and 512KB BurstRAM Secondary Cache Module for PowerPC - Based Systems | Motorola Semiconductors |
| MPC2004 | (MPC2004 / MPC2005) 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms | Motorola Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |