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PDF MCF5407 Data sheet ( Hoja de datos )
| Número de pieza | MCF5407 | |
| Descripción | Microprocessor | |
| Fabricantes | Motorola Semiconductors | |
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mAdvance Information
U.coMCF5407PB/D
t4Rev. 3.3, 2/2003
heeMCF5407 Integrated
SColdFire® Microprocessor
taProduct Brief
www.Da This document is an overview of the MCF5407 ColdFire processor, focusing on feature
menhancements over the MCF5307. It includes general descriptions of features and of the
various modules incorporated in the MCF5407. It describes the V4 programming model as it
ois implemented in the MCF5407.
.c1.1 Features
UThe MCF5407 integrated microprocessor combines a Version 4 ColdFire processor core with
t4the following components, as shown in Figure 1:
• Harvard architecture memory system with 16-Kbyte instruction cache and 8-Kbyte
edata cache
e• Two, 2-Kbyte on-chip SRAMs
h• Integer/fractional multiply-accumulate (MAC) unit
• Divide unit
S• System debug interface
ta• DRAM controller for synchronous and asynchronous DRAM
• Four-channel DMA controller
a• Two general-purpose timers
• Two UARTs, one that supports synchronous operations
.D• I2C™ interface
• Parallel I/O interface
w• System integration module (SIM)
wDesigned for embedded control applications, the MCF5407 delivers 316 Dhrystone MIPS at
w www.DataSheet4U.com220 MHz or 233 Dhrystone MIPS at 162 MHz.
1 page  
MCF5407 Features
— Operand packing and unpacking supported
— Auto-alignment transfers supported for efficient block movement
— Supports bursting and cycle steal
— Provides two bus clock internal access
— Automatic DMA transfers from on-chip UARTs using internal interrupts
• DRAM controller
— Support for synchronous DRAM (SDRAM), extended-data-out (EDO) DRAM, and fast page
mode
— Supports up to 512 Mbytes of DRAM
— Programmable timer provides CAS-before-RAS refresh for asynchronous DRAMs
— Support for two separate memory blocks
• Two UARTs
— One UART offers synchronous mode with expanded buffers for soft modem support
— Full-duplex operation
— Flexible baud-rate generator
— Modem control signals available (CTS, RTS)
— Processor-interrupt capability
• Dual 16-bit general-purpose multiple-mode timers
— 8-bit prescaler
— Timer input and output pins
— Processor-interrupt capability
— Up to 18.5-nS resolution at 54 MHz
• I2C module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, keypads
— Fully compatible with industry-standard I2C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
• System interface module (SIM)
— Chip selects provide direct interface to 8-, 16-, and 32-bit SRAM, ROM, FLASH, and
memory-mapped I/O devices
— Eight, fully-programmable chip selects, each with a base address register
— Programmable wait states and port sizes per chip select
— User-programmable processor clock/input clock frequency ratio
— Programmable interrupt controller
— Low interrupt latency
— Four external interrupt request inputs
— Programmable autovector generator
— Software watchdog timer
MOTOROLA
MCF5407 Integrated ColdFire® Microprocessor Product Brief
5
5 Page 
ColdFire Module Description
1.3.8.3 16-Bit Parallel Port Interface
A 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin
basis.
1.3.8.4 Interrupt Controller
The interrupt controller provides user-programmable control of ten internal peripheral interrupts and
implements four external fixed interrupt-request pins. Each internal interrupt can be programmed to any one
of seven interrupt levels and four priority levels within each of these levels. Additionally, the external
interrupt request pins can be mapped to levels 1, 3, 5, and 7 or levels 2, 4, 6, and 7. Autovector capability is
available for both internal and external interrupts.
1.3.8.5 JTAG
To help with system diagnostics and manufacturing testing, the MCF5407 processor includes dedicated
user-accessible test logic that complies with the IEEE 1149.1a standard for boundary-scan testability, often
referred to as the Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1a
standard.
1.3.9 System Debug Interface
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators. The debug unit contained in the MCF5407 is a compatible
upgrade to the MCF52xx and MCF53xx debug modules with added breakpoint registers and support for I/O
interrupt request servicing while in emulator mode.
The on-chip breakpoint resources include a total of 13 programmable registers—two sets of address
registers (each with two 32-bit registers), two sets of data registers (each with a 32-bit data register plus
32-bit data mask register), one 32-bit PC register plus a 32-bit PC mask register and three additional 32-bit
PC registers. These registers can be accessed through the dedicated debug serial communication channel,
or from the processor's supervisor mode programming model. The breakpoint registers can be configured
to generate triggers by combining the address, data and PC conditions in a variety of single or dual-level
definitions and the trigger event can be programmed to generate a processor halt, or initiate a debug interrupt
exception.
The MCF5407’s new interrupt servicing options during emulator mode allow real-time critical interrupt
service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the Version 4 debug module has combined the processor status and debug data
outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus along with the PSTCLK output provide
execution status, captured operand data and branch target addresses defining processor activity at one-half
the CPU's clock rate.
MOTOROLA
MCF5407 Integrated ColdFire® Microprocessor Product Brief
11
11 Page | ||
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