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PDF PLL205-13 Data sheet ( Hoja de datos )
| Número de pieza | PLL205-13 | |
| Descripción | Motherboard Clock Generator | |
| Fabricantes | PhaseLink | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PLL205-13 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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.com PLL205-13Motherboard Clock Generator for AMD - K7
et4UFEATURES
She• Generates all clock frequencies for VIA K7 chip
tasets requiring multiple CPU clocks and high
aspeed SDRAM buffers.
.D• Support one pair of differential CPU clocks, one
3.3V push-pull CPU, 6 PCI and 13 high-speed
wSDRAM buffers for 3-DIMM applications.
ww• One 24_48MHz clock and one 48MHz clock.
m• Two14.318MHz reference clocks.
• Power management control to stop CPU, and
oPower down Mode from I2C programming.
.c• Support 2-wire I2C serial bus interface with built-
in Vendor ID, Device ID and Revision ID.
• Single byte micro-step linear Frequency Progra-
Umming via I2C with Glitch free smooth switching.
t4• Enhanced CPU and SDRAM output Drive
selected by I2C.
e• Built-in programmable watchdog timer up to 63
seconds with 1-second interval. It will generate a
eLOW reset output when timer expired.
h• Spread Spectrum ±0.25% center spread, 0 to
-0.5% down spread.
S• Available in 300 mil 48 pin SSOP.
taBLOCK DIAGRAM
aXIN
.DXOUT
XTAL
OSC
wFS (0:3)*
ww .comPD
PLL1
SST
Control
Logic
heet4USDATA
SSCLK
PLL2
I2C
Logic
.DataSDRAMIN
÷2
Watch
Dog
VDD1
REF(0:1)
CPUT1
CPUT0
CPUC0
VDD2
PCI(0:4)
PCI5
VDD4
48Mhz
24_48Mhz
WDRESET
VDD3
SDRAM(0:11)
SDRAM12
PIN CONFIGURATION
VDD0
REF0//CPU_STOP#^
GND
XIN
XOUT
VDD1
PCI5/MODE*^
PCI0/FS3*^
GND
PCI1/SEL24_48*^
PCI2
PCI3
PCI4
VDD2
SDRAMIN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 REF1/FS2*^
47 GND
46 CPUT1
45 GND
44 CPUC0
43 CPUT0
42 VDD3
41 PD/WDRESET#
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDD3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDD3
29 SDRAM6
28 SDRAM7
27 VDD4
26 48MHz/FS0*^
25 24_48MHz/FS1*^
Note: ^: Pull up, #: Active Low
*: Bi-directional latched at power-up
I/O MODE CONFIGURATION
MODE (Pin 7)
1 (OUTPUT)
0 (INPUT)
PIN 2
REF0
CPU_STOP
POWER GROUP
• VDD0: PLL CORE
• VDD1: REF(0:1), XIN, XOUT
• VDD2: PCI(0:5)
• VDD3: SDRAM(0:12)
• VDD4: 48MHz, 24_48MHz
KEY SPECIFICATIONS
• CPU Cycle to Cycle jitter: 250ps.
• PCI to PCI output skew: 500ps.
• CPU to CPU output skew: ±175ps
• SDRAM to SDRAM output skew: 250ps.
• CPU to PCI skew (CPU leads): 0 ~ 3 ns.
www47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/23/00 Page 1
1 page  
PLL205-13
Motherboard Clock Generator for AMD - K7
2. BYTE 1: CPU Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default Description
Bit 7 -
17,18,20,21,
Bit 6 28,29,31,32,
34,35,37,38
Bit 5 46
Bit 4 43,44
Bit 3 40
Bit 2 -
Bit 1 43,44
Bit 0 46
1 Reserved
1 High Strength SDRAM Select ( 1=Normal, 0= Enhanced by 25% )
1 Enhanced CPUT1 Drive Select ( 1=Normal, 0=Enhanced by 25% )
1
Enhanced CPUT0, CPUC0 Drive Select
( 1=Normal, 0=Enhanced by 25% )
1 SDRAM12 ( Active/Inactive )
1 Reserved
1 CPUT0, CPUC0 ( Active/Inactive )
1 CPUT1 ( Active/Inactive )
3. BYTE 2: PCI Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default Description
Bit 7 -
Bit 6 7
Bit 5 -
Bit 4 13
Bit 3 12
Bit 2 11
Bit 1 10
Bit 0 8
1 Reserved
1 PCI5 ( Active/Inactive )
1 Reserved
1 PCI4 ( Active/Inactive )
1 PCI3 ( Active/Inactive )
1 PCI2 ( Active/Inactive )
1 PCI1 ( Active/Inactive )
1 PCI0 ( Active/Inactive )
4. BYTE 3: SDRAM Clock Register (1=Enable, 0=Disable)
Bit
Pin#
Default Description
Bit 7 -
Bit 6 -
Bit 5 26
Bit 4 25
Bit 3 17
Bit 2 18
Bit 1 20
Bit 0 21
1 Reserved
1 Reserved
1 48MHz ( Active/Inactive )
1 24_48MHz ( Active/Inactive )
1 SDRAM11 ( Active/Inactive )
1 SDRAM10 ( Active/Inactive )
1 SDRAM9 ( Active/Inactive )
1 SDRAM8 ( Active/Inactive )
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/23/00 Page 5
5 Page 
PLL205-13
Motherboard Clock Generator for AMD - K7
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature
Junction Temperature
ESD Voltage
VDD VSS-0.5
7
V
VI
VSS-0.5
VDD+0.5
V
VO
VSS-0.5
VDD+0.5
V
TS -65 150 °C
TA 0 70 °C
TJ 115 °C
2 KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
2. AC/DC Electrical Specifications
PARAMETERS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Power Down
Pull-up resistor
Operating Supply Current
Input frequency
Input Capacitance
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
PD
Rpu
IDD
FI
CIN
CINX
CONDITIONS
VIN = VDD
Logic inputs without
internal pull-up on
SCLK, VIN = 0V
Logic inputs with
internal pull-up
resistors, VIN = 0V
Pin 2,7,8,10,25,26,48
CL=0 pF @ 66MHz
CL=0 pF @ 100MHz
CL=0 pF @ 133MHz
VDD = 3.3V
Logic Inputs
XIN & XOUT pins
MIN.
2.0
VSS-0.3
-5
TYP.
MAX.
VDD+0.3
0.8
5
UNITS
V
V
µA
µA
-200 µA
600 µA
120 kohm
180 mA
12 14.318 16 MHz
5 pF
27 45 pF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 06/23/00 Page 11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet PLL205-13.PDF ] | |
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