|
|
PDF MT46V64M4 Data sheet ( Hoja de datos )
| Número de pieza | MT46V64M4 | |
| Descripción | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MT46V64M4 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
m 256Mb: x4, x8, x16 DDR SDRAM
o Features
Double eDeat4tUa.c Rate (DDR) SDRAMMT46V64M4 – 16 Meg x 4 x 4 banks
ShMT46V32M8 – 8 Meg x 8 x 4 banks
ataMT46V16M16 – 4 Meg x 16 x 4 banks
.DFor the most current data sheet, please refer to the Micron® Web site: www.micron.com/datasheets
wwFeatures
w• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
m• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
oreceived with data, i.e., source-synchronous data
.ccapture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
U• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
t4• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
e• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
e• Data mask (DM) for masking write data (x16 has two
– one per byte)
h• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
S• Longer-lead TSOP for improved reliability (OCPL)
ta• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option supported
• tRAS lockout supported (tRAP = tRCD)
.DaTable 1: Configuration Addressing
wConfiguration
wRefresh Count
Row Addressing
mBank Addressing
w oColumn Addressing
64 Meg x 4
16 Meg x 4 x 4 banks
8K
8K (A0–A12)
4 (BA0,BA1)
2K (A0–A9,A11)
Options
Marking
• Configuration
64 Meg x 4 (16 Meg x 4 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
16 Meg x 16 (4 Meg x 16 x 4 banks)
• Plastic Package – OCPL
66-pin TSOP
66-pin TSOP (lead-free)
• Plastic Package
60-Ball FBGA (8mm x 14mm)
60-Ball FBGA (8mm x 14mm) lead-free
• Timing – Cycle Time
5ns @ CL = 3 (DDR400B)
6ns @ CL = 2.5 (DDR333) FBGA only
6ns @ CL = 2.5 (DDR333) TSOP only
7.5ns @ CL = 2 (DDR266)
7.5ns @ CL = 2 (DDR266A)
7.5ns @ CL = 2.5 (DDR266B)
• Self Refresh
Standard
Low-Power Self Refresh
• Temperature Rating
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
• Revision
x4, x8
x16
64M4
32M8
16M16
TG
P
FG
BG
-5B
-6
-6T
-75E
-75Z
-75
None
L
None
IT
:G, :C
:C, :F
32 Meg x 8
8 Meg x 8 x 4 banks
8K
8K (A0–A12)
4 (BA0,BA1)
1K (A0–A9)
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0,BA1)
512 (A0–A8)
t4U.cTable 2:
Key Timing Parameters
CL = CAS (READ) Latency; minimum clock rate @ CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and CL = 3 (-5B)
eClock Rate
heSpeed Grade
S-5B
ta-6
6T
a-75E/-75Z
.D-75
CL = 2
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
CL = 2.5
167 MHz
167 MHz
167 MHz
133 MHz
133 MHz
CL = 3
200 MHz
N/A
N/A
N/A
N/A
Data- Out Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
Access Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ Skew
+0.40ns
+0.40ns
+0.45ns
+0.50ns
+0.50ns
w09005aef8076894f
w256MBDDRx4x8x16_1.fm - Rev. K 5/05 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
wProducts and specifications discussed herein are subject to change by Micron without notice.
1 page  
256Mb: x4, x8, x16 DDR SDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
256Mb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Functional Block Diagram: 64 Meg x 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Block Diagram: 32 Meg x 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Functional Block Diagram: 16 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin Assignment (Top View) 66-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
60-Ball FBGA Ball Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . .26
READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE to READ - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
WRITE to READ – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
WRITE to READ – Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
WRITE to PRECHARGE - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
WRITE to PRECHARGE – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
WRITE to PRECHARGE – Odd Number of Data – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Data Output Timing – tAC and tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Initialize and Load Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Bank Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Bank Read - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Bank Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Bank Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Write – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
66-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
60-Ball FBGA (8x14mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
09005aef8076894f
256MBDDRx4x8x16LOF.fm - Rev. K 5/05 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
5 Page 
256Mb: x4, x8, x16 DDR SDRAM
Pin/Ball Assignments and Descriptions
Table 4: Ball/Pin Descriptions (Continued)
FBGA
Numbers
TSOP
Numbers
A8, B7, C7,
D7, D3, C3,
B3, A2
2, 5, 8,
11, 56, 59,
62, 65
B1, B9, C1, C9, 4, 7, 10, 13,
D1, D9, E1, 14, 16, 17, 20,
E7, E9, F7 25, 43, 53, 54,
57, 60, 63,
B7, D7, D3,
B3
5, 11, 56,
62
B1, B9, C1, C9, 4, 7, 10, 13,
D1, D9, E1, 14, 16, 17, 20,
E7, E9, F7, 25, 43, 53, 54,
57, 60, 63,
A2, A8, C3, C7 2, 8, 59, 65
Symbol
DQ0–DQ2
DQ3–DQ5
DQ6, DQ7
NC
DQ0–DQ2
DQ3
NC
NF
E3 51 DQS
E7 16 LDQS
E3 51 UDQS
F9
B2, D2, C8,
E8, A9
A1, C2, E2,
B8, D8
F8, M7, A7
A3, F2, M3
F1
17, 19, 50
3, 9, 15,
55, 61
6, 12, 52,
58, 64
1, 18, 33
34, 48, 66
49
DNU
VDDQ
VSSQ
VDD
VSS
VREF
Type Description
I/O Data Input/Output: Data bus for x8.
– No Connect for x8
These pins should be left unconnected.
I/O Data Input/Output: Data bus for x4.
– No Connect for x4
These pins should be left unconnected.
–
I/O
–
Supply
Supply
No Function for x4
These pins should be left unconnected.
Data Strobe: Output with read data, input with write data. DQS is
edge-aligned with read data, centered in write data. It is used to
capture data. For the x16, LDQS is DQS for DQ0–DQ7 and UDQS is
DQS for DQ8–DQ15. Pin 16 (E7) is NC on x4 and x8.
Do Not Use: Must float to minimize noise on VREF.
DQ Power Supply: +2.5V ±0.2V (+2.6V ±0.1V for DDR400). Isolated
on the die for improved noise immunity.
DQ Ground: Isolated on the die for improved noise immunity.
Supply
Supply
Supply
Power Supply: +2.5V ±0.2V (+2.6V ±0.1V for DDR400).
Ground.
SSTL_2 reference voltage.
Table 5:
Reserved NC Balls and Pins
NC pins not listed may also be reserved for other uses; this table defines NC pins of importance
FBGA
NUMBERS
F9
TSOP
NUMBERS
17
SYMBOL
A13
TYPE DESCRIPTION
I Address input A13 for 1Gb devices. DNU for FBGA.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. K 5/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT46V64M4.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MT46V64M16 | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | Micron Technology |
| MT46V64M4 | (MT46Vxxx) DOUBLE DATA RATE DDR SDRAM | Micron Technology |
| MT46V64M8 | Double Data Rate (DDR) SDRAM | Micron Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |