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PDF HT95Lxxx Data sheet ( Hoja de datos )
| Número de pieza | HT95Lxxx | |
| Descripción | LCD Type Phone 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT95LXXX
LCD Type Phone 8-Bit MCU
Features
· Provide MASK type and OTP type version
· Operating voltage range: 2.4V~5.5V
· Program ROM
- HT95L400/40P: 16K´16 bits
- HT95L300/30P: 8K´16 bits
- HT95L200/20P: 8K´16 bits
- HT95L100/10P: 4K´16 bits
- HT95L000/00P: 4K´16 bits
· Data RAM
- HT95L400/40P: 2880´8 bits
- HT95L300/30P: 2112´8 bits
- HT95L200/20P: 1152´8 bits
- HT95L100/10P: 1152´8 bits
- HT95L000/00P: 384´8 bits
· Bidirectional I/O lines
- HT95L400/40P: 40~28 I/O lines
- HT95L300/30P: 28~16 I/O lines
- HT95L200/20P: 28~20 I/O lines
- HT95L100/10P: 20~16 I/O lines
- HT95L000/00P: 18~14 I/O lines
· 16-bit table read instructions
· Subroutine nesting
- HT95L400/40P: 12 levels
- HT95L300/30P: 8 levels
- HT95L200/20P: 8 levels
- HT95L100/10P: 8 levels
- HT95L000/00P: 4 levels
· Timer
- Two 16-bit programmable Timer/Event Counter
- Real time clock (RTC)
- Watchdog Timer (WDT)
· Programmable frequency divider (PFD)
Supported for HT95L400/40P, HT95L300/30P,
HT95L200/20P, HT95L100/10P
· Dual system clock: 32768Hz, 3.58MHz
· Four operating modes: Idle mode, Sleep mode,
Green mode and Normal mode
· Up to 1.117ms instruction cycle with 3.58MHz system
clock
· All instructions in one or two machine cycles
· Built-in 3.58MHz DTMF Generator
· Built-in dialer I/O
· Built-in low battery detector
Supported for HT95L400/40P, HT95L300/30P,
HT95L200/20P, HT95L100/10P
· LCD driver
- LCD contrast can be adjusted by software or exter-
nal resistor
- Support two LCD frame frequency 64Hz, 128Hz
- Support 16 or 8 common driver pins
- Some segments or commons can option to
bidirectional I/O lines
- HT95L400/40P: 48 seg.´16 com.
- HT95L300/30P: 48 seg.´16 com.
- HT95L200/20P: 24 seg.´16 com.
- HT95L100/10P: 20 seg.´8 com.
- HT95L000/00P: 16 seg.´8 com.
· HT95L400/40P: 128-pin QFP package
HT95L300/30P: 100-pin QFP package
HT95L200/20P: 100-pin QFP package
HT95L100/10P: 64-pin QFP package
HT95L000/00P: 56-pin SSOP package
Applications
· Deluxe Feature Phone
· Caller ID Phone
· Cordless Phone
· Fax and answering machines
· Other communication system
General Description
The HT95LXXX family MCU are 8-bit high performance
RISC-like microcontrollers with built-in DTMF generator
and dialer I/O which provide MCU dialer implementation
or system control features for telecom product applica-
tions. The phone controller has a built-in program ROM,
data RAM, LCD driver and I/O lines for high end prod-
ucts design. In addition, for power management pur-
pose, it has a built-in frequency up conversion circuit
(32768Hz to 3.58MHz) which provides dual system
clock and four types of operation modes. For example, it
can operate with low speed system clock rate of
32768Hz in green mode with little power consumption. It
can also operate with high speed system clock rate of
3.58MHz in normal mode for high performance opera-
tion. To ensure smooth dialer function and to avoid MCU
shut-down in extreme low voltage situation, the dialer
I/O circuit is built-in to generate hardware dialer signals
such as on-hook, hold-line and hand-free. Built-in real
time clock and programmable frequency divider are pro-
vided for additional fancy features in product develop-
ments. The device is best suited for feature phone
products that comply with versatile dialer specification
requirements of different areas or countries.
Rev. 1.20
1 May 26, 2004
1 page  
HT95L100/10P, HT95L000/00P
COM 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
XM U TE
DNPO
64 63 62 61 60 59 58 57 56 55 54 53 52
1 51
2 50
3 49
4 48
5 47
6 46
7 45
8 44
9 H T 9 5 L 1 0 0 /1 0 P
1 0 6 4 Q F P -A
11
43
42
41
12 40
13 39
14 38
15 37
16 36
17 35
18 34
19 33
20 21 22 23 24 25 26 27 28 29 30 31 32
SEG 6
SEG 7
SEG 8
SEG 9
S E G 10
S E G 11
S E G 12
S E G 13
S E G 14
S E G 15
S E G 1 6 /P E 0
S E G 1 7 /P E 1
S E G 1 8 /P E 2
S E G 1 9 /P E 3
V LC D
M U S IC
RES
TM R 0
D TM F
HT95LXXX
PA3
PA2
PA1
PA0
PB5
PB4
VSS
PB3
PB2
PB1
PB0
IN T
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
SEG 0
SEG 1
SEG 2
SEG 3
SEG 4
SEG 5
SEG 6
SEG 7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 P A 4
55 P A 5
54 P A 6
53 P A 7
52 X 1
51 X 2
50 X C
49 N C
48 V D D
47 R E S
46 D TM F
45 N C
44 N C
43 H FI
42 H FO
41 X M U TE
40 D N P O
39 P O
38 H K S
37 N C
3 6 S E G 1 5 /P E 3
3 5 S E G 1 4 /P E 2
3 4 S E G 1 3 /P E 1
3 3 S E G 1 2 /P E 0
32 S E G 11
31 S E G 10
30 S E G 9
29 S E G 8
H T 9 5 L 0 0 0 /0 0 P
5 6 S S O P -A
Pin Description
Pin Name
CPU
I/O
VDD
VSS
X1
X2
XC
RES
¾
¾
I
O
I
I
INT I
INT/TMR1
I
TMR0
I
Description
Positive power supply
Negative power supply, ground
A 32768Hz crystal (or resonator) should be connected to this pin and X2.
A 32768Hz crystal (or resonator) should be connected to this pin and X1.
External low pass filter used for frequency up conversion circuit.
Schmitt trigger reset input, active low.
Supported for HT95L000/00P
Schmitt trigger input for external interrupt
No internal pull-high resistor.
Edge trigger activated on a falling edge.
Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P
Schmitt trigger input for external interrupt or Timer/Event Counter 1.
No internal pull-high resistor.
For INT: Edge trigger activated on a falling edge.
For TMR1: Activated on falling or rising transition edge, selected by software.
Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P
Schmitt trigger input for Timer/Event Counter 0.
No internal pull-high resistor.
Activated on falling or rising transition edge, selected by software.
Rev. 1.20
5 May 26, 2004
5 Page 
HT95LXXX
Stack Register
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 12 levels (HT95L400/40P), 8 lev-
els (HT95L300/30P, HT95L200/20P, HT95L100/10P) or
4 levels (HT95L000/00P) and is neither part of the data
nor part of the program space, and is neither readable
nor writable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writable. At a
subroutine call or interrupt acknowledge signal, the con-
tents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, sig-
naled by a return instruction (RET or RETI), the program
counter is restored to its previous value from the stack.
After a chip reset, the SP will point to the top of the stack.
If the stack is full and an interrupt takes place, the inter-
rupt request flag will be recorded but the acknowledge
signal will be inhibited even if this interrupt is enabled.
When the stack pointer is decremented (by RET or
RETI), the interrupt will be serviced. This feature pre-
vents stack overflow allowing the programmer to use the
structure more easily. If the stack is full and a ²CALL² is
subsequently executed, stack overflow occurs and the
first entry will be lost (only the most recent 12, 8 or 4, de-
pending on various MCU type, returned addresses are
stored).
Data Memory
The data memory is divided into four functional groups:
special function registers, embedded control register,
LCD display memory and general purpose memory.
Most are read/write, but some are read only.
The special function registers are located from 00H to
1FH. The embedded control registers are located in the
memory areas from 20H to 3FH. The remaining spaces
which are not specified in the following table before the
40H are reserved for future expanded usage and read-
ing these locations will get ²00H². The general purpose
data memory is divided into 15 banks (HT95L400/40P),
11 banks (HT95L300/30P), 6 banks (HT95L200/20P,
HT95L100/10P) or 2 banks (HT95L000/00P). The
banks in the RAM are all addressed from 40H to 0FFH
and they are selected by setting the value of the bank
pointer (BP).
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1). The
bank1~bank14 and bank27 are only indirectly accessi-
ble through memory pointer 1 register (MP1).
The LCD display memory is located at bank 1BH. They
can be read and written to by the indirect addressing
mode using memory pointer 1 (MP1). To turn the display
On or Off, a ²1² or ²0² is written to the corresponding bit
of the memory area.
Special Register, Embedded Control Register, LCD Display Memory and General Purpose RAM
BP
(RAM Bank)
Address
Function
Description
Supported for HT95LXXX
400/P 300/P 200/P 100/P 000/P
Special Function Register
00H 00H IAR0 Indirect addressing register 0
ÖÖÖÖÖ
00H 01H MP0 Memory pointer register 0
ÖÖÖÖÖ
00H 02H IAR1 Indirect addressing register 1
ÖÖÖÖÖ
00H 03H MP1 Memory pointer register 1
ÖÖÖÖÖ
00H 04H
BP Bank Pointer register
ÖÖÖÖÖ
00H 05H
ACC Accumulator
ÖÖÖÖÖ
00H 06H
PCL Program counter lower-order byte register Ö Ö Ö Ö Ö
00H 07H TBLP Table pointer
ÖÖÖÖÖ
00H 08H TBLH Table higher-order byte register
ÖÖÖÖÖ
00H
09H
WDTS Watchdog Timer option setting register
ÖÖÖÖÖ
00H
0AH
STATUS Status register
ÖÖÖÖÖ
00H
0BH
INTC0 Interrupt control register 0
ÖÖÖÖÖ
00H
0CH
TMR0H
Timer/Event Counter 0 high-order byte
register
ÖÖÖÖÖ
Rev. 1.20
11 May 26, 2004
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT95Lxxx.PDF ] | |
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