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PDF HT95L100 Data sheet ( Hoja de datos )
| Número de pieza | HT95L100 | |
| Descripción | (HT95L100/10P) 8-Bit LCD Type Phone Controller MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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Preliminary
HT95L100/10P
8-Bit LCD Type Phone Controller MCU
Features
· Provide MASK type and OTP type version
· Operating voltage range: 2.4V~5.5V
· Program ROM: 4K´16 bits
· Data RAM: 1152´8 bits
· Up to 20 bidirectional I/O lines
· 16-bit table read instructions
· Eight-level subroutine nesting
· Timer:
- Two 16-bit programmable Timer/Event Counter
- Real time clock (RTC)
- Watchdog Timer (WDT)
· Programmable frequency divider (PFD)
· Dual system clock: 32768Hz, 3.58MHz
· Four operating modes: Idle mode, Sleep mode,
Green mode and Normal mode
· Up to 1.117ms instruction cycle with 3.58MHz system
clock
· Built-in 3.58MHz DTMF Generator
· LCD driver:
- 20 seg.´8 com.
- 4 segments can per nibble option to bidirectional
I/O lines
- LCD contrast can be adjusted by software or exter-
nal resistor
- Fixed frame frequency 64Hz
· Built-in Low Battery detector
· All instructions in one or two machine cycles
· Built-in dialer I/O
· 64-pin QFP package
Applications
· Deluxe Feature Phone
· Caller ID Phone
· Cordless Phone
· Fax and answering machines
· Other communication system
General Description
The HT95L100/10P are 8-bit high performance
RISC-like microcontrollers with built-in DTMF generator
and dialer I/O which provide MCU dialer implementation
or system control features for telecom product applica-
tion. The phone controller has a built-in program ROM,
data RAM, LCD driver and a maximum of 20 I/O lines for
high end products design. In addition, for power man-
agement purpose, it has a built-in frequency up conver-
sion circuit (32768Hz to 3.58MHz) which provides dual
system clock and four types of operation modes. For ex-
ample it can operate with low speed system clock rate of
32768Hz in green mode with little power consumption. It
can also operate with high speed system clock rate of
3.58MHz in normal mode for high performance opera-
tion. To ensure smooth dialer function and to avoid MCU
shut-down in extreme low voltage situation, the dialer
I/O circuit is built-in to generate hardware dialer signals
such as on-hook, hold-line and hand-free. Built-in real
time clock and programmable frequency divider are pro-
vided for additional fancy features in product develop-
ments. The device is best suitable for feature phone
products that comply with versatile dialer specification
requirements of different areas or countries.
Rev. 0.10
1 October 1, 2002
1 page  
Preliminary
HT95L100/10P
Electrical Characteristics
Ta=25°C
Symbol
CPU
Parameter
IIDL Idle Mode Current
ISLP Sleep Mode Current
IGRN
Green Mode Current
INOR
Normal Mode Current
VIL I/O Port Input Low Voltage
VIH I/O Port Input High Voltage
IOL I/O Port Sink Current
IOH I/O Port Source Current
RPH Pull-high Resistor
LBIN
Low Battery Detection
Reference Voltage
LCD Driver
VLCD
LCD Panel Power Supply
ILCD LCD Operation Current
Dialer I/O
IXMO
XMUTE Leakage Current
IOLXM
XMUTE Sink Current
IHKS HKS Input Current
RHFI
HFI Pull-low Resistance
RHDI
HDI Pull-high Resistance
IOH2 HFO Source Current
IOL2 HFO Sink Current
IOH3 HDO Source Current
IOL3 HDO Sink Current
IOH4 PO Source Current
IOL4 PO Sink Current
IOL5 DNPO Sink Current
DTMF Generator
VTDC
DTMF Output DC Level
VTOL
DTMF Sink Current
VTAC
DTMF Output AC Level
RL DTMF Output Load
ACR Column Pre-emphasis
THD
Tone Signal Distortion
Test Conditions
VDD Conditions
Min. Typ. Max. Unit
32768Hz off, 3.58MHz off,
5V CPU off, LCD off, WDT off,
no load
32768Hz on, 3.58MHz off,
5V CPU off, LCD off, WDT off,
no load
32768Hz on, 3.58MHz off,
5V CPU on, LCD off, WDT off,
no load
32768Hz on, 3.58MHz on,
5V CPU on, LCD on, WDT on,
DTMF generator off, no load
5V ¾
5V ¾
5V ¾
5V ¾
5V ¾
¾
¾
¾
¾
0
4
4
-2
10
¾2
¾ 30
¾ 50
¾3
¾1
¾5
6¾
-3 ¾
30 ¾
5V ¾
1.10 1.15 1.20
mA
mA
mA
mA
V
V
mA
mA
kW
V
¾¾
¾ VLCD=5V, 32768Hz, no load
¾
¾
35
¾ 100
V
mA
2.5V XMUTE pin=2.5V
2.5V XMUTE pin=0.5V
2.5V HKS pin=2.5V
2.5V VHFI=2.5V
2.5V VHDI=0V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOH=2V
2.5V VOL=0.5V
2.5V VOL=0.5V
¾¾1
mA
1
¾¾
mA
¾
¾ 0.1
mA
¾ 200 ¾
kW
¾ 200 ¾
kW
-1 ¾ ¾ mA
1
¾¾
mA
-1 ¾ ¾ mA
1
¾¾
mA
-1 ¾ ¾ mA
1
¾¾
mA
1
¾¾
mA
¾¾
¾ VDTMF=0.5V
¾ Row group, RL=5kW
¾ THD£-23dB
¾ Row group=0dB
¾ RL=5kW
0.45VDD ¾ 0.7VDD V
0.1 ¾ ¾ mA
120 155 180 mVrms
5
¾¾
kW
1 2 3 dB
¾ -30 -23 dB
Rev. 0.10
5 October 1, 2002
5 Page 
Preliminary
HT95L100/10P
Register
INTC0
(0BH)
INTC1
(1EH)
Bits Label R/W
Function
0 EMI RW Controls the master (global) interrupt (1=enabled; 0=disabled)
1 EEI RW Controls the external interrupt (1=enabled; 0=disabled)
2 ET0I RW Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
3 ET1I RW Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
4 EIF RW External interrupt request flag (1=active; 0=inactive)
5 T0F RW Timer/Event Counter 0 request flag (1=active; 0=inactive)
6 T1F RW Timer/Event Counter 1 request flag (1=active; 0=inactive)
7 ¾ RO Unused bit, read as ²0²
0 ¾ RO Unused bit, read as ²0²
1 ERTCI RW Control the real time clock interrupt (1=enable; 0=disable)
2 EDRI RW Control the dialer I/O interrupt (1=enable; 0=disable)
3 ¾ RO Unused bit, read as ²0²
4 ¾ RO Unused bit, read as ²0²
5 RTCF RW Internal real time clock interrupt request flag (1=active; 0=inactive)
6 DRF RW Internal dialer I/O interrupt request flag (1=active: 0=inactive)
7 ¾ RO Unused bit, read as ²0²
The Timer/Event Counter 1 interrupt is generated by a
timeout overflow and the interrupt request flag T1F will
be set. When the Timer/Event Counter 1 interrupt is en-
abled, the stack is not full and the T1F bit is set, a sub-
routine call to location 0CH will occur. The interrupt
request flag T1F and EMI bits will be cleared to disable
further interrupts.
The real time clock interrupt is generated by a 1Hz RTC
generator. When the RTC time-out occurs, the interrupt
request flag RTCF will be set. When the RTC interrupt is
enabled, the stack is not full and the RTCF is set, a sub-
routine call to location 14H will occur. The interrupt re-
quest flag RTCF and EMI bits will be cleared to disable
other interrupts.
The dialer I/O interrupt is triggered by any edge transi-
tion onto HKS pin or a falling edge transition onto HDI
pin or a rising edge transition onto HFI pin, the interrupt
request flag DRF will be set. When the dialer I/O inter-
rupt is enabled, the stack is not full and the DRF is set, a
subroutine call to location 18H will occur. The interrupt
request flag DRF and EMI bits will be cleared to disable
other interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority Vector
External interrupt
1 04H
Timer/Event Counter 0 interrupt 2
08H
Timer/Event Counter 1 interrupt 3
0CH
Real time clock interrupt
4 14H
Dialer I/O interrupt
5 18H
Priority of the interrupt
EMI, EEI, ET0I, ET1I, ERTCI and EDRI are used to con-
trol the enabling/disabling of interrupts. These bits pre-
vent the requested interrupt from being serviced. Once
the interrupt request flags (EIF, T0F, T1F, RTCF, DRF)
are set by hardware or software, they will remain in the
INTC0 or INTC1 registers until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be dam-
aged once the ²CALL² operates in the interrupt subrou-
tine.
Rev. 0.10
11 October 1, 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT95L100.PDF ] | |
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