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PDF LT1719 Data sheet ( Hoja de datos )
| Número de pieza | LT1719 | |
| Descripción | 4ns/ 150MHz Dual Comparator with Independent Input/Output Supplies | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LT1719
4.5ns Single/Dual Supply
3V/5V Comparator with
Rail-to-Rail Output
FEATURES
s UltraFast: 4.5ns at 20mV Overdrive
7ns at 5mV Overdrive
s Low Power: 4.2mA at 3V
s Separate Input and Output Power Supplies
s Output Optimized for 3V and 5V Supplies
s Input Voltage Range Extends 100mV
Below Negative Rail
s TTL/CMOS Compatible Rail-to-Rail Output
s Low Power Shutdown Mode: 0.1µA
U
APPLICATIO S
s High Speed Differential Line Receiver
s Crystal Oscillator Circuits
s Level Translators
s Threshold Detectors/Discriminators
s Zero-Crossing Detectors
s High Speed Sampling Circuits
s Delay Lines
TYPICAL APPLICATION
2.7V to 6V Crystal Oscillator with TTL/CMOS Output
2.7V TO 6V
2k
1MHz TO 10MHz
CRYSTAL (AT-CUT)
220Ω
620Ω
GROUND
+ CASE
C1
LT1719
–
2k
0.01µF
1.8k
OUTPUT
1719 TA01
DESCRIPTIO
The LT®1719 is an UltraFastTM comparator optimized for low
voltage operation. Separate supplies allow flexible operation
to accomodate separate analog input ranges and output logic
levels. The input voltage range extends from 100mV below
VEE to 1.2V below VCC. Internal hysteresis makes the LT1719
easy to use even with slow moving input signals. The rail-to-
rail outputs directly interface to TTL and CMOS. Alternatively
the symmetric output drive can be harnessed for analog
applications or for easy translation to other single supply
logic levels.
The LT1719 is available in the 8-pin SO package; a shutdown
control allows for reduced power consumption and extended
battery life in portable applications.
For a dual/quad comparator with similar performance, see
the LT1720/LT1721.
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
Propagation Delay vs Overdrive
8
7
6
RISING EDGE
(tPDLH)
5
25°C
VSTEP = 100mV
VCC = 5V
CLOAD = 10pF
4
FALLING EDGE
3 (tPDHL)
2
1
0
0 10 20 30 40 50
OVERDRIVE (mV)
1719 TA02
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
LT1719
Output Low Voltage
vs Load Current
0.5
+VS = 5V
VIN = – 10mV
0.4 125°C
VCC = 2.7V
125°C
0.3
– 55°C
25°C
0.2
0.1
0
4 8 12 16
OUTPUT SINK CURRENT (mA)
20
1719 G10
Shutdown Currents
vs Shutdown Voltage
5.0
150
SUPPLY CURRENT
4.5
4.0
3.5
100 3.0
2.5
SHDN
50 PIN CURRENT
2.0
1.5
1.0
0.5
0
(VS – 4V) (VS – 3V) (VS – 2V) (VS – 1V)
SHDN PIN VOLTAGE (V)
0
VS
1719 G13
Output High Voltage
vs Load Current
0.0
125°C
– 0.2
+VS = 5V
VIN = 10mV
– 55°C
– 0.4 25°C
– 0.6
– 0.8
– 1.0
0
25°C
VCC = 2.7V
4 8 12 16
OUTPUT SOURCE CURRENT (mA)
20
1719 G11
Shutdown Currents
vs Temperature
10 SHUTDOWN = +VS – 0.5V
1
+IS
SHUTDOWN
PIN
CURRENT
+IS
SHUTDOWN PIN OPEN
0.1
VCC = +VS = 5V
VEE = – 5V
–50 –25
0 25 50 75 100 125 150
TEMPERATURE (°C)
1719 G14
Supply Current vs Frequency
9
25°C
8 + VS = 5V
7
CLOAD = 20pF
6
5 CLOAD = 10pF
4
NO LOAD
3
2
0 10 20 30 40
FREQUENCY (MHz)
1719 G12
Wake-Up Delay
vs Temperature
700
600
500
400
300
200
100
– 50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
1719 G15
TEST CIRCUITS
PULSE
0V IN
–3V
0V
0.1µF
1N5711
Response Time Test Circuit
–100mV
25Ω
130Ω
25Ω
2N3866
50k
V1* 50Ω
+Vs – VCM
VCC – VCM
0.01µF
1
2+ 8
DUT
3
LT1719
–5
4
7
6
0.01µF
VEE – VCM
50Ω 400Ω 750Ω
–VCM
*V1 = –1000 • (OVERDRIVE + VTRIP+)
NOTE: RISING EDGE TEST SHOWN.
–5V FOR FALLING EDGE, REVERSE LT1719 INPUTS
10 × SCOPE PROBE
(CIN ≈ 10pF)
1719 TC02
5
5 Page 
LT1719
APPLICATIONS INFORMATION
5V
180Ω
LSTTL 270Ω
5V
10KH/E
DO NOT USE FOR LT1719
LEVEL TRANSLATION. SEE TEXT
820Ω
(a) STANDARD TTL TO PECL TRANSLATOR
VCC +VS
LT1719
R2
R1
R3
VEE
(b) LT1719 OUTPUT TO PECL TRANSLATOR
VCC 3V
VECL
LT1719
R2
R1
R4 R3
VEE
(c) 3V LT1719 OUTPUT TO PECL TRANSLATOR
VCC +VS
+ VS R1 R2 R3
10KH/E 5V OR 5.2V 510Ω 180Ω 750Ω
100K/E 4.5V 620Ω 180Ω 510Ω
VECL
R1 R2 R3 R4
10KH/E 5V OR 5.2V 300Ω 180Ω OMIT 560Ω
100K/E 4.5V 330Ω 180Ω 1500Ω 1000Ω
LT1719
R4
R1
R2 R3
VEE VECL
(d) LT1719 OUTPUT TO STANDARD ECL TRANSLATOR
ECL FAMILY VECL + VS R1 R2 R3 R4
10KH/E
– 5.2V 5V 560Ω 270Ω 330Ω 1200Ω
3V 270Ω 510Ω 300Ω 330Ω
100K/E
– 4.5V 5V 680Ω 270Ω 300Ω 1500Ω
3V 330Ω 390Ω 270Ω 430Ω
1719 F06
Figure 6
evaluated carefully. Note that there is some degradation of
noise margin due to the ±5% resistor selections shown.
With 10KH/E, there is no temperature compensation of the
logic levels, whereas the LT1719 and the circuits shown
give levels that are stable with temperature. This will lower
the noise margin over temperature. In some configura-
tions it is possible to add compensation with diode or
transistor junctions in series with the resistors of these
networks.
For more information on ECL design, refer to the ECLiPS
data book (DL140), the 10KH system design handbook
(HB205) and PECL design (AN1406), all from Motorola.
Circuit Description
The block diagram of the LT1719 is shown in Figure 7. The
circuit topology consists of a differential input stage, a
gain stage with hysteresis and a complementary com-
mon-emitter output stage. All of the internal signal paths
utilize low voltage swings for high speed at low power.
The input stage topology maximizes the input dynamic
range available without requiring the power, complexity
and die area of two complete input stages such as are
found in rail-to-rail input comparators. With a single 2.7V
supply, the LT1719 still has a respectable 1.6V of input
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet LT1719.PDF ] | |
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