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PDF MC68306 Data sheet ( Hoja de datos )

Número de pieza MC68306
Descripción Integrated EC000 Processor
Fabricantes Motorola Semiconductors　
Logotipo Motorola Semiconductors Logotipo



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MC68306
Integrated EC000 Processor
User’s Manual
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not
convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims,
costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
µunintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
© MOTOROLA, 1993

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MC68306 pdf
TABLE OF CONTENTS (Continued)
Paragraph
Number
Title
Page
Number
2.3 DRAM Controller Signals........................................................................................ 2-9
2.3.1 Column Address Strobe (CAS1–CAS0 )............................................................... 2-9
2.3.2 Row Address Strobe (RAS1 –RAS0) .................................................................... 2-9
2.3.3 DRAM Write Signal (DRAMW) ............................................................................. 2-9
2.4 Interrupt Control and Parallel Port Signals ............................................................. 2-9
2.4.1 Interrupt Request (IRQ7–IRQ1) ........................................................................... 2-9
2.4.2 Interrupt Acknowledge (IACK7–IACK1) ............................................................... 2-9
2.4.3 Port A Signals (PA7–PA0) ................................................................................... 2-9
2.4.4 Port B (PB7–PB0) ................................................................................................ 2-9
2.5 Clock and Mode Control Signals ............................................................................ 2-10
2.5.1 Crystal Oscillator (EXTAL, XTAL) ........................................................................ 2-10
2.5.2 Clock Out (CLKOUT) ........................................................................................... 2-10
2.5.3 Address Mode (AMODE) ..................................................................................... 2-10
2.6 Serial Module Signals ............................................................................................. 2-10
2.6.1 Channel A Receiver Serial-Data Input (RxDA) .................................................... 2-10
2.6.2 Channel A Transmitter Serial-Data Output (TxDA) ............................................. 2-10
2.6.3 Channel B Receiver Serial-Data Input (RxDB) .................................................... 2-10
2.6.4 Channel B Transmitter Serial-Data Output (TxDB) ............................................. 2-10
2.6.5 CTSA ................................................................................................................... 2-11
2.6.6 RTSA ................................................................................................................... 2-11
2.6.7 CTSB ................................................................................................................... 2-11
2.6.8 RTSB ................................................................................................................... 2-11
2.6.9 Crystal Oscillator (X1, X2) ................................................................................... 2-11
2.6.10 IP2 ..................................................................................................................... 2-11
2.6.11 OP3 ................................................................................................................... 2-11
2.7 JTAG Port Test Signals .......................................................................................... 2-11
2.7.1 Test Clock (TCK) ................................................................................................. 2-12
2.7.2 Test Mode Select (TMS)...................................................................................... 2-12
2.7.3 Test Data In (TDI) ................................................................................................ 2-12
2.7.4 Test Data Out (TDO) ........................................................................................... 2-12
2.7.5 Test Reset (TRST) .............................................................................................. 2-12
Section 3
68000 Bus Operation Description
3.1 Data Transfer Operations ....................................................................................... 3-1
3.1.1 Read Cycle .......................................................................................................... 3-1
3.1.2 Write Cycle .......................................................................................................... 3-4
3.1.3 Read-Modify-Write Cycle..................................................................................... 3-7
3.1.4 CPU Space Cycle ................................................................................................ 3-11
vi
MC68306 USER'S MANUAL
MOTOROLA

5 Page





MC68306 arduino
LIST OF ILLUSTRATIONS
Figure
Number
Title
Page
Number
Figure 1-1. MC68306 Simplified Block Diagram....................................................... 1-1
Figure 2-1. MC68306 Detailed Block Diagram ......................................................... 2-2
Figure 3-1. Word Read Cycle Flowchart .................................................................. 3-2
Figure 3-2. Byte Read Cycle Flowchart .................................................................... 3-2
Figure 3-3. Read and Write Cycle Timing Diagram .................................................. 3-3
Figure 3-4. Word and Byte Read Cycle Timing Diagram ......................................... 3-3
Figure 3-5. Word Write Cycle Flowchart ................................................................... 3-5
Figure 3-6. Byte Write Cycle Flowchart .................................................................... 3-6
Figure 3-7. Word and Byte Write Cycle Timing Diagram.......................................... 3-6
Figure 3-8. Read-Modify-Write Cycle Flowchart ....................................................... 3-8
Figure 3-9. Read-Modify-Write Cycle Timing Diagram ............................................. 3-9
Figure 3-10. Interrupt Acknowledge Cycle ............................................................... 3-11
Figure 3-11. Interrupt Acknowledge Cycle Timing Diagram ..................................... 3-12
Figure 3-12. Three-Wire Bus Arbitration Cycle Flowchart ........................................ 3-13
Figure 3-13. Two-Wire Bus Arbitration Cycle Flowchart ........................................... 3-14
Figure 3-14. Three-Wire Bus Arbitration Timing Diagram ........................................ 3-15
Figure 3-15. Two-Wire Bus Arbitration Timing Diagram ........................................... 3-15
Figure 3-16. External Asynchronous Signal Synchronization ................................... 3-17
Figure 3-17. Bus Arbitration Unit State Diagrams..................................................... 3-19
Figure 3-18. Three-Wire Bus Arbitration Timing Diagram—Processor Active .......... 3-20
Figure 3-19. Three-Wire Bus Arbitration Timing Diagram—Bus Inactive ................. 3-21
Figure 3-20. Three-Wire Bus Arbitration Timing Diagram—Special Case ............... 3-22
Figure 3-21. Two-Wire Bus Arbitration Timing Diagram—Processor Active ............ 3-23
Figure 3-22. Two-Wire Bus Arbitration Timing Diagram—Bus Inactive .................... 3-24
Figure 3-23. Two-Wire Bus Arbitration Timing Diagram—Special Case .................. 3-25
Figure 3-24. Bus Error Timing Diagram .................................................................... 3-26
Figure 3-25. Retry Bus Cycle Timing Diagram ......................................................... 3-27
Figure 3-26. Halt Operation Timing Diagram............................................................ 3-28
Figure 3-27. Reset Operation Timing Diagram......................................................... 3-29
Figure 3-28 Fully Asynchronous Read Cycle ........................................................... 3-32
Figure 3-29. Fully Asynchronous Write Cycle........................................................... 3-32
Figure 3-30. Pseudo-Asynchronous Read Cycle ..................................................... 3-33
Figure 3-31. Pseudo-Asynchronous Write Cycle...................................................... 3-34
Figure 3-32. Synchronous Read Cycle..................................................................... 3-36
Figure 3-33. Synchronous Write Cycle ..................................................................... 3-37
xii
MC68306 USER'S MANUAL
MOTOROLA

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