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PDF LT1533IS Data sheet ( Hoja de datos )

Número de pieza LT1533IS
Descripción Ultralow Noise 1A Switching Regulator
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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FEATURES
s Greatly Reduced Conducted and Radiated EMI
(<100µVP-P in Typical Application)
s Low Switching Harmonic Content
s Independent Control of Switch Voltage and
Current Slew Rates
s Two 1A Current Limited Power Switches
s Regulates Positive and Negative Voltages
s 20kHz to 250kHz Oscillator Frequency
s Easily Synchronized to External Clock
s Wide Input Voltage Range: 2.7V to 23V
s Low Shutdown Current: 12µA Typical
s Easier Layout than with Conventional Switchers
s Outputs Can Be Forced to 50% Duty Cycle for
Unregulated Applications
U
APPLICATIONS
s Precision Instrumentation Systems
s Isolated Supplies for Industrial Automation
s Medical Instruments
s Wireless Communications
s Single Board Data Acquisition Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
LT1533
Ultralow Noise
1A Switching Regulator
DESCRIPTION
The LT®1533 is a new class of switching regulator designed
to reduce conducted and radiated electromagnetic interfer-
ence (EMI). Ultralow noise and EMI are achieved by providing
user control of the output switch slew rates. Voltage and
current slew rates can be independently programmed to
optimize switcher harmonic content versus efficiency. The
LT1533 can reduce high frequency harmonic power by as
much as 40dB with only minor losses in efficiency.
The LT1533 utilizes a dual output switch current mode
architecture optimized for low noise topologies. The IC
includes two 1A power switches along with all necessary
oscillator, control and protection circuitry. Unique error amp
circuitry can regulate both positive and negative voltages.
The internal oscillator may be synchronized to an external
clock for more accurate placement of switching harmonics.
Protection features include cycle by cycle current limit pro-
tection, undervoltage lockout and thermal shutdown.
Low minimum supply voltage and low supply current during
shutdown make the LT1533 well suited for portable applica-
tions. The part may also be forced into a 50% duty cycle mode
for unregulated applications. The LT1533 is available in the
16-pin narrow SO package.
TYPICAL APPLICATION
Low Noise 5V to 12V Forward Push-Pull DC/DC Converter
+
0.015µF
5V
14
33µF 11 VIN 2
SHDN
COL A
820pF
16.9k
3
DUTY
15
4
SYNC
COL B
5 CT
16
PGND
LT1533
13
6 RT
RVSL
12
RCSL
15k 10
7
VC GND
FB
NFB
1000pF 9
8
T1 1N4148
L1
300µH
L2
B 33µH A
Note 1
1N4148 + C1 +
47µF
16V
15k
15k
21.5k, 1%
1533 TA01
2.49k
1%
C1: SANYO OS-CON
C2: AVX TPS TANTALUM
L1: COILTRONICS CTX300-2
L2: COILCRAFT DT1608C-333
T1: COILTRONICS CTX02-13834
NOTE 1: 25nH TRACE INDUCTANCE
OR COILCRAFT B07T
12V
150mA
12V Output Noise (BW = 100MHz)
C2
33µF
20V
A
100µV/DIV
< 100µVP-P
B
2mV/DIV
2µs/DIV
1533 TA02
1

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LT1533IS pdf
LT1533
PIN FUNCTIONS
COL A, COL B (Pins 2, 15): These are the output collectors
of the power switches. Their emitters return to PGND
through a common sense resistor. COL A and
COL B are alternately turned on out of phase. Large
currents flow into these pins so it is desirable to keep
external trace lengths short to minimize radiation. The
collectors can be tied together for simple boost applica-
tions.
DUTY (Pin 3): Tying the DUTY pin to ground will force the
outputs to switch with a 50% duty cycle. The DUTY pin
must float if not used.
SYNC (Pin 4): The SYNC pin can be used to synchronize
the oscillator to an external clock (see Oscillator Sync in
Applications Information section for more details). The
SYNC pin may either be floated or tied to ground if not
used.
CT (Pin 5): The oscillator capacitor pin is used in conjunc-
tion with RT to set the oscillator frequency. For RT = 16.9k,
CT(NF) = 129/fOSC(kHz)
RT (Pin 6): The oscillator resistor pin is used to set the
charge and discharge currents of the oscillator capacitor.
The nominal value is 16.9k. It is possible to adjust this
resistance ±25% to get a more accurate oscillator fre-
quency.
FB (Pin 7): The feedback pin is used for positive voltage
sensing and oscillator frequency shifting during start-up
and short-circuit conditions. It is the inverting input to the
error amplifier. The noninverting input of this amplifier
connects internally to a 1.25V reference. This pin should
be left open if not used.
NFB (Pin 8): The negative voltage feedback pin is used for
sensing a negative output voltage. The pin is connected to
the inverting input of the negative feedback amplifier
through a 100k source resistor. The negative feedback
amplifier provides a gain of – 0.5 to the feedback amplifier.
The nominal regulation point would be – 2.5V on NFB. This
pin should be left open if not used.
GND (Pin 9): Signal Ground. The internal error amplifier,
negative feedback amplifier, oscillator, slew control cir-
cuitry and the bandgap reference are referred to this
ground. Keep the connection to the feedback divider and
VC compensation network free of large ground currents.
VC (Pin 10): The compensation pin is used for frequency
compensation and current limiting. It is the output of the
error amplifier and the input of the current comparator.
Loop frequency compensation can be performed with an
RC network connected from the VC pin to ground.
SHDN (Pin 11): The shutdown pin is used for disabling the
switcher. Grounding this pin will disable all internal cir-
cuitry. Normally this output can be tied high (to VIN) or may
be left floating.
RCSL (Pin 12): A resistor to ground sets the current slew
rate for the collectors A and B. The minimum resistor value
is 3.9k and the maximum value is 68k. Current slew will be
approximately:
ISLEW(A/µs) = 33/RCSL(k)
RVSL (Pin 13): A resistor to ground sets the voltage slew
rate for the collectors A and B. The minimum resistor value
is 3.9k and the maximum value is 68k. Voltage slew will be
approximately:
VSLEW(V/µs) = 220/RVSL(k)
VIN (Pin 14): Input Supply Pin. Bypass this pin with a
4.7µF low ESR capacitor. When VIN is below 2.55V the
part will go into undervoltage lockout where it will stop
output switching and pull the VC pin low.
PGND (Pin 16): Power Switch Ground. This ground comes
from the emitters of the power switches. In normal opera-
tion this pin should have approximately 25nH inductance
to ground. This can be done by trace inductance (approxi-
mately 1") or with wire or a specific inductive component.
This inductance ensures stability in the current slew
control loop during turn-off. Too much inductance (>50nH)
may produce oscillation on the output voltage slew edges.
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LT1533IS arduino
LT1533
APPLICATIONS INFORMATION
RVC
2k
CVC
0.01µF
VC PIN
CVC2
4.7nF
1533 F03
turns ratio of the transformer. The turns ratio must be
large enough to ensure that the transformer can put out a
voltage equal to the output voltage plus the diode under
minimum input conditions.
Figure 3
To prevent irregular switching, VC pin ripple should be
kept below 50mVP-P. Worst-case VC pin ripple occurs at
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047µF capacitor on the VC pin reduces
switching frequency ripple to only a few millivolts. A low
value for RVC will also reduce VC pin ripple, but loop phase
margin may be inadequate.
Magnetics
Design of magnetics is dependent on topology. The fol-
lowing details the design of the magnetics for a push-pull
converter. In this converter the transformer usually stores
little energy. The following equations should be consid-
ered as the starting point to building a prototype.
VIN
Q1A
Q1B
T1
1:N
DS1 VSEC
LO
DS2
+ VOUT
CO
1533 F04
Figure 4
The following definitions will be used:
VIN = Input supply voltage
VSW = Switch-on voltage
VOUT = Desired output voltage
IOUT = Output current
f = Oscillator frequency
VF = Forward drop of the rectifier
Duty cycle is the major defining equation for this topology.
Note that the output L and C basically filter the chopped
voltage so duty cycle controls output voltage. N is the
( )N = VOUT + VF
2 DCMAX VIN(MIN) VSW
DCMAX is the maximum duty cycle of each driver with
respect to the entire cycle which consists of two periods
(Q1A on and Q1B on). So the effective duty cycle is
2 • DCMAX. The controller, in general, determines maxi-
mum duty cycle. A 44% maximum duty cycle is a guaran-
teed value for this part.
Some Common Turns Ratios
VIN
VOUT
N
5 ±10%
12
3.6
5 ±10%
15
4.4
5 ±10%
3.3
1.1
Remember to add sufficient margin in the turns ratio to
account for IR drops in the transformer windings, worst-
case diode forward drop (VF) and switch-on voltage (VSW).
There are a number of ways to choose the inductance
value for LO. We suggest as a starting point that LO be
selected such that the converter is continuous at
IOUT(MAX)/4. If your minimum IOUT is higher than this, or
you are operating at low currents such that the IC and
components can handle higher peak currents, then use a
higher number.
Continuous operation occurs when the current in the
inductor never goes to zero. Discontinuous operation
occurs when the inductor current drops to zero before the
start of the next cycle and can occur with small inductors
and light loads. There is nothing inherently bad about
discontinuous operation, however, the converter control
and operation is somewhat different. The inductor is
smaller for discontinuous operation but the peak currents
in the switch, the transformer, the diodes, inductor and
capacitor will be higher. But for low power situations these
may not present a big constraint.
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