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PDF SST39VF160Q Data sheet ( Hoja de datos )
| Número de pieza | SST39VF160Q | |
| Descripción | 16 Megabit (1M x 16-Bit) Multi-Purpose Flash | |
| Fabricantes | Silicon Storage Technology | |
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16 Megabit (1M x 16-Bit) Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
FEATURES:
• Organized as 1 M X 16
• Single 2.7V-only Read and Write Operations
• VDDQ Power Supply to Support 5V I/O
for SST39VF160Q
- VDDQ not available on SST39VF160
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Current: 15 mA (typical)
- Standby Current: 3 µA (typical)
- Auto Low Power Mode: 3 µA (typical)
• Small Sector Erase Capability (512 sectors)
- Uniform 2 KWord sectors
• Block Erase Capability (32 blocks)
- Uniform 32 KWord blocks
• Fast Read Access Time:
- 70 and 90 ns
• Latched Address and Data
• Fast Sector Erase and Word Program:
- Sector Erase Time: 3 ms typical
- Block Erase Time: 7 ms typical
- Chip Erase Time: 15 ms typical
- Word Program time: 7 µs typical
- Chip Rewrite Time: 7 seconds
• Automatic Write Timing
- Internal Vpp Generation
• End of Write Detection
- Toggle Bit
- Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
- EEPROM Pinouts and command set
• Packages Available
- 48-Pin TSOP (12mm x 20mm)
- 6 x 8 Ball TFBGA
PRODUCT DESCRIPTION
The SST39VF160Q/VF160 devices are 1M x 16 CMOS
Multi-Purpose Flash (MPF) manufactured with SST’s
proprietary, high performance CMOS SuperFlash tech-
nology. The split-gate cell design and thick oxide tunnel-
ing injector attain better reliability and manufacturability
compared with alternate approaches. The
SST39VF160Q/VF160 write (Program or Erase) with a
2.7V-only power supply. The SST39VF160Q/VF160
conform to JEDEC standard pinouts for x16 memories.
Featuring high performance word program, the
SST39VF160Q/VF160 devices provide a maximum
word-program time of 10 µsec. The entire memory can
typically be erased and programmed word by word in 7
seconds, when using interface features such as Toggle
Bit or Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, the
SST39VF160Q/VF160 have on-chip hardware and soft-
ware data protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, the
SST39VF160Q/VF160 are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39VF160Q/VF160 devices are suited for appli-
cations that require convenient and economical updating
of program, configuration, or data memory. For all sys-
tem applications, the SST39VF160Q/VF160 signifi-
cantly improve performance and reliability, while lower-
ing power consumption. The SST39VF160Q/VF160 in-
herently use less energy during Ease and Program than
alternative flash technologies. The total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed
during any Erase or Program operation is less than
alternative flash technologies. The SST39VF160Q/
VF160 also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of endurance
cycles that have occurred. Therefore the system
software or hardware does not have to be modified or
de-rated as is necessary with alternative flash technolo-
gies, whose erase and program times increase with
accumulated endurance cycles.
To meet high density, surface mount requirements, the
SST39VF160Q/VF160 are offered in 48-pin TSOP and
48-pin TFBGA packages. See Figures 1 and 2 for
pinouts.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write sequences.
A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first.
© 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc.
329-09 11/98
1 These specifications are subject to change without notice.
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1 page  
16 Megabit Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
A19-A0
Address Inputs
DQ15-DQ0 Data Input/output
CE#
OE#
WE#
VDD
VDDQ
Chip Enable
Output Enable
Write Enable
Power Supply
I/O Power Supply
Vss Ground
NC No Connection
Functions
To provide memory addresses. During sector erase A19-A11 address lines
will select the sector. During block erase A19-A15 address lines will select
the block.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations.
To provide 3-volt supply (2.7-3.6V)
Supplies power for input/output buffers. It should be either tied to VDD
(2.7 - 3.6V) for 3V I/O or to a 5.0V (4.5V - 5.5V) power supply to
support 5V I/O. (Not offered on SST39VF160 device, instead it is a NC)
Unconnected pins.
329 PGM T2.6
TABLE 3: OPERATION MODES SELECTION
Mode
CE# OE#
Read
VIL VIL
Program
VIL VIH
Erase
VIL VIH
Standby
Write Inhibit
Write Inhibit
Product Identification
Hardware Mode
VIH X
X VIL
XX
VIL VIL
Software Mode
VIL VIL
WE#
VIH
VIL
VIL
X
X
VIH
VIH
VIH
A9 DQ
AIN DOUT
AIN DIN
XX
X High Z
X High Z/ DOUT
X High Z/ DOUT
Address
AIN
AIN
Sector or block address,
XXh for chip erase
X
X
X
VH Manufacturer Code (00BF) A19 - A1 = VIL, A0 = VIL
Device Code (2782)
A19 - A1 = VIL, A0 = VIH
AIN See Table 4
329 PGM T3.2
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© 1998 Silicon Storage Technology, Inc.
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329-09 11/98
5 Page 
16 Megabit Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
ADDRESS A19-0
CE#
OE#
WE#
DQ15-0
VIH
HIGH-Z
TRC
TAA
TCE
TOE
TOLZ
TCLZ
TOH
DATA VALID
FIGURE 3: READ CYCLE TIMING DIAGRAM
TOHZ
TCHZ
DATA VALID
HIGH-Z
329 ILL F03.1
ADDRESS A19-0
WE#
TAS
OE#
CE#
DQ15-0
5555
TAH
TWP
2AAA
TWPH
5555
TCH
XXAA
TCS
XX55
XXA0
ADDR
TDS
DATA
INTERNAL PROGRAM OPERATION STARTS
TBP
TDH
SW0
SW1
SW2
WORD
(ADDR/DATA)
329 ILL F04.1
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
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© 1998 Silicon Storage Technology, Inc.
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329-09 11/98
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet SST39VF160Q.PDF ] | |
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