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PDF ST72T311 Data sheet ( Hoja de datos )
| Número de pieza | ST72T311 | |
| Descripción | 8-BIT MCU WITH 8 TO 16K OTP/EPROM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST72T311 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ST72E311
ST72T311
8-BIT MCU WITH 8 TO 16K OTP/EPROM,
384 TO 512 BYTES RAM, ADC, WDG, SCI, SPI AND 2 TIMERS
DATASHEET
s User Program Memory (OTP/EPROM):
8 to 16K bytes
s Data RAM: 384 to 512 bytes including 256 bytes
of stack
s Master Reset and Power-On Reset
s Low Voltage Detector Reset option
s Run and Power Saving modes
s 44 or 32 multifunctional bidirectional I/O lines:
– 15 or 9 programmable interrupt inputs
– 8 or 4 high sink outputs
PSDIP42
CSDIP42W
– 8 or 6 analog alternate inputs
– 13 alternate functions
– EMI filtering
s Software or Hardware Watchdog (WDG)
s Two 16-bit Timers, each featuring:
– 2 Input Captures 1)
– 2 Output Compares 1)
– External Clock input (on Timer A)
PSDIP56
CSDIP56W
– PWM and Pulse Generator modes
s Synchronous Serial Peripheral Interface (SPI)
s Asynchronous Serial Communications Interface
(SCI)
s 8-bit ADC with 8 channels 2)
s 8-bit Data Manipulation
s 63 basic Instructions and 17 main Addressing
Modes
s 8 x 8 Unsigned Multiply Instruction
s True Bit Manipulation
s Complete Development Support on DOS/
WINDOWSTM Real-Time Emulator
s Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
TQFP64
TQFP44
(See ordering information at the end of datasheet)
Notes:
1. One only on Timer A.
2. Six channels only for ST72T311J.
Device Summary
Features
ST72T311J2
ST72T311J4
ST72T311N2
ST72T311N4
Program Memory - bytes
8K
16K
8K
16K
RAM (stack) - bytes
384 (256)
512 (256)
384 (256)
512 (256)
Peripherals
Watchdog, Timers, SPI, SCI, ADC and optional Low Voltage Detector Reset
Operating Supply
3 to 5.5 V
CPU Frequency
8MHz max (16MHz oscillator) - 4MHz max over 85°C
Temperature Range
- 40°C to + 125°C
Package
TQFP44 - SDIP42
TQFP64 - SDIP56
Note: The ROM versions are supported by the ST72314 family.
September 1999
Rev. 1.7
1/100
1
1 page  
1.2 PIN DESCRIPTION
Figure 2. 64-Pin Thin QFP Package Pinout
ST72E311 ST72T311
Figure 4. 44-Pin Thin QFP Package Pinout
PE4
PE5
PE6
PE7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
1 64 63 62 61 60 59 58 5756 55 54 53 52 51 50 4498
2 47
3 (EI0) 46
4 (EI0) 45
5 (EI2)
(EI0) 44
6 (EI2)
(EI0) 43
7 (EI2)
42
8 (EI2)
9 (EI3)
41
40
10 (EI3)
39
11 (EI3)
38
12 (EI3)
13
37
36
14 35
15 34
16
17
18
19
20
21
2
2
23
24
25
26
27
28
29
3
0
31
3233
VSS _1
VDD _1
PA3
PA2
PA1
PA0
PC7/SS
PC6/SCK
PC5/MOSI
PC4/MISO
PC3/ICAP1_B
PC2/ICAP2_B
PC1/OCMP1_B
PC0/OCMP2_B
VSS _0
VDD _0
PE1/RDI
PB0
PB1
PB2
PB3
PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
44 43 42 41 40 39 38 37 36 35 34
1 33
2 (EI2)
32
3 (EI2)
(EI0) 31
4 (EI2)
30
5 (EI2)
29
6 (EI3)
28
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
VS S_1
VD D_ 1
PA3
PC7/SS
PC6/SCK
PC5/MOSI
PC4/MISO
PC3/ICAP1_B
PC2/ICAP2_B
PC1/OCMP1_B
PC0/OCMP2_B
1. V on EPR OM/OTP only
PP
Figure 3. 56-Pin Shrink DIP Package Pinout
PB4
PB5
PB6
PB7
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
AIN5/PD5
AIN6/PD6
AIN7/PD7
VDD A
VSSA
CLKOUT/PF0
PF1
PF2
OCMP1_A/PF4
ICAP1_A/PF6
EXTCLK_A/PF7
VDD_ 0
VSS _0
PC0/OCMP2_B
PC1/OCMP1_B
PC2/ICAP2_B
PC3/ICAP1_B
PC4/MISO
PC5/MOSI
1. V on EPROM/OTP only
PP
1 (EI3)
2 (EI3)
3 (EI3)
4 (EI3)
5
6
7
8
9
10
11
12
13
14
15 (EI1)
16 (EI1)
17 (EI1)
18
19
20
21
22
23
24
25
26
27
28
(EI2) 56
(EI2) 55
(EI2) 54
(EI2) 53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
(EI0) 34
(EI0) 33
(EI0) 32
(EI0) 31
30
29
PB3
PB2
PB1
PB0
PE7
PE6
PE5
PE4
PE1/RDI
PE0/TD0
VDD _2
OSCIN
OSCOUT
VSS_2
RESET
TEST/ VPP 1)
PA7
PA6
PA5
PA4
VS S_ 1
VD D_ 1
PA3
PA2
PA1
PA0
PC7/SS
PC6/SCK
1. V on EPROM/OTP only
PP
Figure 5. 42-Pin Shrink DIP Package Pinout
PB4
AIN0/PD0
AIN1/PD1
AIN2/PD2
AIN3/PD3
AIN4/PD4
AIN5/PD5
VD DA
VS SA
CLKOUT/PF0
PF1
PF2
OCMP1_A/PF4
ICAP1_A/PF6
EXTCLK_A/PF7
PC0/OCMP2_B
PC1/OCMP1_B
PC2/ICAP2_B
PC3/ICAP1_B
PC4/MISO
PC5/MOSI
1 (EI3)
2
3
4
5
6
7
8
9
10 (EI1)
11 (EI1)
12 (EI1)
13
14
15
16
17
18
19
20
21
(EI2) 42
(EI2) 41
(EI2) 40
(EI2) 39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
(EI0)24
23
22
PB3
PB2
PB1
PB0
PE1/RDI
PE0/TD0
VD D_ 2
OSCIN
OSCOUT
VS S_ 2
RESET
TEST/V
1)
PP
PA7
PA6
PA5
PA4
VS S_ 1
VD D_ 1
PA3
PC7/SS
PC6/SCK
1. V on EPROM/OTP only
PP
5/100
5
5 Page 
Table 4. Hardware Register Memory Map
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h to
001Fh
0020h
0021h
0022h
0023h
0024h to
0029h
002Ah
002Bh
002Ch to
0030h
Block
Port A
Port C
Port B
Port E
Port D
Port F
SPI
WDG
Register
Label
PADR
PADDR
PAOR
PCDR
PCDDR
PCOR
PBDR
PBDDR
PBOR
PEDR
PEDDR
PEOR
PDDR
PDDDR
PDOR
PFDR
PFDDR
PFOR
Register Name
Data Register
Data Direction Register
Option Register
Reserved Area (1 byte)
Data Register
Data Direction Register
Option Register
Reserved Area (1 byte)
Data Register
Data Direction Register
Option Register
Reserved Area (1 byte)
Data Register
Data Direction Register
Option Register
Reserved Area (1 byte)
Data Register
Data Direction Register
Option Register
Reserved Area (1 byte)
Data Register
Data Direction Register
Option Register
Reserved Area (9 bytes)
MISCR
SPIDR
SPICR
SPISR
Miscellaneous Register
SPI Data I/O Register
SPI Control Register
SPI Status Register
Reserved Area (6 bytes)
WDGCR
WDGSR
Watchdog Control Register
Watchdog Status Register
Reserved Area (5 bytes)
ST72E311 ST72T311
Reset
Status
00h
00h
00h
Remarks
R/W
R/W
R/W 1)
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W
00h R/W 1)
00h R/W
00h R/W
0Ch R/W 1)
00h R/W
00h R/W
00h R/W 1)
00h R/W
00h R/W
28h R/W 1)
00h
xxh R/W
xxh R/W
00h Read Only
7Fh R/W
00h R/W3)
11/100
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST72T311.PDF ] | |
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