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PDF SP8607 Data sheet ( Hoja de datos )
| Número de pieza | SP8607 | |
| Descripción | emitter coupled logic divider | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SP8607 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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1 page  
OPERATING NOTES
1. The clock inputs (pins 1 and 2) can be driven single ended or
differentially and should be capacitively coupled to the signal
source. The input signal path is completed by connecting a
capacitor from the internal bias decoupling, pin 3, to ground.
2. In the absence of a signal the device will self-oscillate. If this is
undesirable, it may be prevented by connecting a 15kΩ resistor
from the unused input to VEE. This will reduce the input sensitivity
by approximately 100mV.
SP8607
3. The circuit will operate down to DC but slew rate must be better
than 100V/µs.
4. The outputs are compatible with ECLII. There is an internal load
of 4kΩ on each output. The outputs can be interfaced to ECL10K
by the addition of 1·5kΩpulldown resistors from the outputs to VEE
to increase output voltage swing.
5. Input impedance is a function of frequency, See Fig. 4.
6. All components should be suitable for the frequency in use.
GENERATOR
INPUT
TO SAMPLING
SCOPE
2·7k 1n
1n 3 5
16
450 10n
OUTPUT
33
33
DUT
27
450 10n
OUTPUT
8
20
1n
3·5k 3·5k
VEE
1n
Fig. 5 Test circuit
INPUT
1n
1
15k
1n
440
2
5
DIVIDE BY
440 2
BIAS
4k 4k
6
7
8
1n
Fig. 6 Typical application showing interfacing
ECL OUTPUT
1·5k 1·5k
VEE
3
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet SP8607.PDF ] | |
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