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PDF LT1325 Data sheet ( Hoja de datos )
| Número de pieza | LT1325 | |
| Descripción | Microprocessor-Controlled Battery Management System | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC1325
Microprocessor-Controlled
Battery Management System
FEATURES
s Fast Charge Nickel-Cadmium, Nickel-Metal-Hydride,
Lithium Ion or Lead-Acid Batteries under µP Control
s Flexible Current Regulation:
– Programmable 111kHz PWM Current Regulator
with Built-In PFET Driver
– PFET Current Gating for Use with External Current
Regulator or Current Limited Transformer
s Discharge Mode
s Measures Battery Voltage, Battery Temperature and
Ambient Temperature with Internal 10-Bit ADC
s Battery Voltage, Temperature and Charge Time
Fault Protection
s Built-In Voltage Regulator and Programmable
Battery Attenuator
s Easy-to-Use 3- or 4-Wire Serial µP Interface
s Accurate Gas Gauge Function
s Wide Supply Range: VDD = 4.5V to 16V
s Can Charge Batteries with Voltages Greater Than VDD
s Can Charge Batteries from Charging Supplies Greater
Than VDD
s Digital Input Pins Are High Impedance in
Shutdown Mode
U
APPLICATIONS
s System Integrated Battery Charger
DESCRIPTION
The LTC®1325 provides the core of a flexible, cost-effec-
tive solution for an integrated battery management sys-
tem. The monolithic CMOS chip controls the fast charging
of nickel-cadmium, nickel-metal-hydride, lead-acid or
lithium batteries under microprocessor control. The de-
vice features a programmable 111kHz PWM constant
current source controller with built-in FET driver, 10-bit
ADC, internal voltage regulator, discharge-before-charge
controller, programmable battery voltage attenuator and
an easy-to-use serial interface.
The chip may operate in one of five modes: power shut-
down, idle, discharge, charge or gas gauge. In power
shutdown the supply current drops to 30µA and in the idle
mode, an ADC reading may be made without any switching
noise affecting the accuracy of the measurement. In the
discharge mode, the battery is discharged by an external
transistor while the battery is being monitored by the
LTC1325 for fault conditions. The charge mode is termi-
nated by the µP while monitoring any combination of
battery voltage and temperature, ambient temperature
and charge time. The LTC1325 also monitors the battery
for fault conditions before and during charging. In the gas
gauge mode the LTC1325 allows the total charge leaving
the battery to be calculated.
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION Battery Charger for up to 8 NiCd or NiMH Cells
+ C2
10µF
P1
IRF9730
MPU
(e.g. 8051)
p1.4
p1.3
p1.2
+ CREG
4.7µF
R1
R2
R3
R4
LTC1325
1 REG
2
DOUT
3
DIN
4
CS
5 CLK
6 LTF
7 MCV
8 HTF
9 GND
VDD 18
PGATE 17
DIS 16
VBAT 15
TBAT 14
TAMB 13
VIN 12
SENSE 11
FILTER 10
R13
100Ω
C1
+ CREG
0.1µF
22µF THERM 2
CF
1µF
R5
THERM 1
D1
1N6818
L1
62µH
RTRK
RDIS
BAT
N1
IRFZ34
RSENSE
VDD
4.5V TO 16V
LTC1325 • TA01
1
1 page  
TYPICAL PERFORMANCE CHARACTERISTICS
PGATE Rise Time vs
Load Capacitance
1200
1000
800
600
TA = 27°C
TA = 70°C
400 TA = 0°C
200
0
0 2 4 6 8 10 12 14 16 18 20
LOAD CAPACITANCE (nF)
1325 G10
Discharge Rise and Fall Time
vs Load Capacitance
14
TA = 70°C
12 TA = 27°C
TA = 0°C
10
RISE TIME
8
6
FALL TIME
4
2
0
0 2 4 6 8 10 12 14 16 18 20
LOAD CAPACITANCE (nF)
1325 G13
Oscillator Frequency vs
Temperature
118
117
116
115
114
113
112
111
110
109
108
–40 –20
0 20 40 60
TEMPERATURE (°C)
80 100
1325 G16
PGATE Fall Time vs
Load Capacitance
1000
900
800
TA = 27°C
700
600
TA = 70°C
500
400
TA = 0°C
300
200
100
0
0 2 4 6 8 10 12 14 16 18 20
LOAD CAPACITANCE (nF)
LTC1325 G11
Minimum Charging Supply vs
Number of Cells
16
RSENSE = 0.15, VR1 = 1,VR0 = 1
14 L = 10µH TO 100µH
IRF9Z30PFET, 1N5819 DIODE
12
10
8
6
RSENSE = 1, VR1 = 1, VR0 = 1
L = 25µH TO 100µH
4 IRF9Z30PFET, 1N5819 DIODE
2 TA = 27°C, NiCd BATTERIES
VCELL = 1.4V NOMINAL
0
12 3 45
6
NUMBER OF CELLS
78
1325 G14
CLK to DOUT Enable Delay Time
vs Temperature
500
450
400
350
300
250
200
150
100
50
0
0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
1325 G17
LTC1325
Differential Nonlinearity
1.0
VDD = 12V
fCLK = 500kHz
0.5
0
–0.5
–1.0
0
128 256 384 512 640 768 896 1024
CODE
1325 G12
Integral Nonlinearity
1.0
VDD = 12V
fCLK = 500kHz
0.5
0
–0.5
–1.0
0
128 256 384 512 640 768 896 1024
CODE
1325 G15
CLK to DOUT Valid Delay Time
vs Temperature
700
600
DOUT GOING HIGH
500
DOUT GOING LOW
400
300
200
100
0
0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
1325 G18
5
5 Page 
LTC1325
FUNCTIONAL DESCRIPTIO
Bit 13: Power Shutdown (PS)
PS selects between the normal operating mode, or the
shutdown mode.
PS DESCRIPTION
0 Normal Operation
1 Shutdown All Circuits Except Digital Inputs
Bits 14 to 16: Duty Ratio Select (DR0 to DR2)
DR2, DR1 and DR0 select the duty cycle of the charging
loop operation (not 111kHz PWM duty cycle). The last
three selections place the chip into a test mode and should
not be used.
DR2 DR1 DR0 DESCRIPTION
0 0 0 1/16
0 0 1 1/8
0 1 0 1/4
0 1 1 1/2
1 0 01
1 0 1 Test Mode 1
1 1 0 Test Mode 2
1 1 1 Test Mode 3
Bits 21 and 22: Charging Loop Reference Voltage
Select (VR0 and VR1)
VR1 and VR0 select the desired reference voltage VCHRG
for the charging loop. The charging loop will force the
average voltage at the Sense pin to be equal to VDAC. The
average charging current is VDAC/RSENSE (see Figure 4).
VR1 VR0 VDAC (mV)
0 0 18
0 1 34
1 0 55
1 1 160
STATUS WORD
The status word is 8 bits long and contains the status of
the internal fail-safe circuits.
12345678
BATP BATR FMCV FEDV FHTF FLTF tOUT FS
LTC1325 • F02
Figure 2. Status Word
Bit 17: Fail-Safe Latch Clear (FSCLR)
When FSCLR bit is set to one, the internal fail-safe timer is
reset to 0, and the fail-safe latches are reset. FSCLR is
automatically reset to 0 when CS goes high.
FSCLR
0
1
DESCRIPTION
No Action
Reset Fail-Safe Timer and Latches
Bits 18 to 20: Timeout Period Select (TO0 to TO2)
TO2, TO1 and TO0 select the desired fail-safe timeout
period,tOUT. On power-up, the default timeout is 5 minutes.
TO2 TO1 TO0 TIMEOUT (MINUTES)
0 0 05
0 0 1 10
0 1 0 20
0 1 1 40
1 0 0 80
1 0 1 160
1 1 0 320
1 1 1 Indefinite (No Timeout)
Bit 1: Battery Present (BATP)
The BATP bit = 1 indicates the presence of the battery. The
bit is set to 1 when the voltage at the VBAT pin falls below
(VDD – 1.8V). BATP = 0 when the battery is removed and
VBAT is pulled high by RTRK (see Figure 3).
BATP
0
1
CONDITIONS
(VDD – 1.8) < VBAT < VDD
VBAT < (VDD – 1.8)
Bit 2: Battery Reversed (BATR) or Shorted
The BATR bit indicates when the battery is connected
backwards or shorted. The bit is set when the battery cell
voltage at the output of the battery divider VCELL is below
100mV.
BATR
0
1
CONDITIONS
VCELL > 100mV
VCELL < 100mV
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LT1325.PDF ] | |
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