PDF CY7C09169 Data sheet ( Hoja de datos )

Número de pieza	CY7C09169
Descripción	(CY7C09159 / CY7C09169) 8K/16K x 9 Synchronous Dual-Port Static RAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! 51 fax id: 5218 PRELIMINARY CY7C09159 CY7C09169 8K/16K x 9 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta- neous access of the same memory location • 2 Flow-Through/Pipelined devices — 8K x 9 organization (CY7C09159) — 16K x 9 organization (CY7C09169) • 3 Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • 0.35-micron CMOS for optimum speed/power • High-speed clock to data access 6.5/7.5/12 ns (max.) • Low operating power — Active= 200 mA (typical) — Standby= 0.05 mA (typical) • Fully synchronous interface for easier operation • Burst counters increment addresses internally — Shorten cycle times — Minimize bus noise — Supported in Flow-Through and Pipelined modes • Dual Chip Enables for easy depth expansion • Automatic power-down • Commercial and Industrial temperature ranges • Available in 100-pin TQFP v Logic Block Diagram R/WL OEL R/WR OER CE0L CE1L 1 0 0/1 1 CE0R 0 CE1R 0/1 FT/PipeL I/O0L–I/O8L 10 0/1 9 [1] A0–A12/13L CLKL ADSL CNTENL CNTRSTL 13/14 Counter/ Address Register Decode Note: 1. A0–A12 for 8K; A0–A13 for 16K. I/O Control I/O Control True Dual-Ported RAM Array 01 0/1 9 FT/PipeR I/O0R–I/O8R Counter/ Address Register Decode 13/14 [1] A0–A12/13R CLKR ADSR CNTENR CNTRSTR For the most recent information, visit the Cypress web site at www.cypress.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 November 1997 - Revised June 5, 1998 1 page PRELIMINARY CY7C09159 CY7C09169 Electrical Characteristics Over the Operating Range CY7C09159 CY7C09169 -6 -7 -12 Symbol Parameter Min Typ Max Min Typ Max Min Typ Max Units VOH Output HIGH Voltage (VCC=Min, 2.4 2.4 2.4 IOH=–4.0 mA) V VOL Output LOW Voltage (VCC=Min, IOH= +4.0 mA) 0.4 0.4 0.4 V VIH Input HIGH Voltage 2.2 2.2 2.2 V VIL Input LOW Voltage 0.8 0.8 0.8 V IOZ Output Leakage Current −10 10 −10 10 −10 10 µA ICC Operating Current Com’l. (VCC=Max, IOUT=0 mA) Indust. Outputs Disabled 250 450 235 420 260 445 195 300 225 375 mA mA ISB1 Standby Current (Both Ports TTL Level)[4] CEL & CER ≥ VIH, f=fMAX Com’l. Indust. ISB2 Standby Current (One Port Com’l. TTL Level)[4] CEL \| CER ≥ VIH, f=fMAX Indust. ISB3 Standby Current (Both Com’l. Ports CMOS Level)[4] CEL & CER ≥ VCC – 0.2V, f=0 Indust. ISB4 Standby Current (One Port Com’l. CMOS Level)[4] CEL \| CER ≥ VIH, f=fMAX Indust. 45 115 175 235 0.05 0.25 160 200 40 105 55 120 160 220 175 235 0.05 0.25 0.05 0.25 145 185 160 200 30 85 45 100 125 190 140 205 0.05 0.25 0.05 0.25 110 150 125 165 mA mA mA mA mA mA mA mA Capacitance Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF AC Test Loads 5V OUTPUT C = 30 pF R1 = 893Ω R2 = 347Ω OUTPUT RTH = 250Ω C = 30 pF OUTPUT VTH = 1.4V C = 5 pF 5V R1 = 893Ω R2 = 347Ω (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES (c) Three-State Delay (Load 2) (Used for tCKLZ, tOLZ, & tOHZ including scope and jig) 3.0V GND 10% 90% 90% 10% Note: ≤ 3 ns ≤ 3 ns 4. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH). 5 5 Page PRELIMINARY CY7C09159 CY7C09169 Switching Waveforms (continued) Pipelined Read with Address Counter Advance[17] CLK tSA ADDRESS tSAD ADS tCYC2 tCH2 tCL2 tHA An tHAD CNTEN tSAD tSCN tHCN tCD2 tSCN DATAOUT Qx-1 Qx Qn READ EXTERNAL tDC READ WITH COUNTER ADDRESS Flow-Through Read with Address Counter Advance[17] tHAD Qn+1 tHCN COUNTER HOLD Qn+2 Qn+3 READ WITH COUNTER CLK ADDRESS tSA tSAD ADS tCYC1 tCH1 tCL1 tHA An tHAD CNTEN tSCN DATAOUT tHCN tCD1 Qx tDC READ EXTERNAL ADDRESS Qn tSAD tHAD tSCN tHCN Qn+1 Qn+2 READ WITH COUNTER Qn+3 COUNTER HOLD READ WITH COUNTER Note: 17. CE0 and OE = VIL; CE1, R/W and CNTRST = VIH. 11 11 Page

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