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PDF MC74HC03A Data sheet ( Hoja de datos )
| Número de pieza | MC74HC03A | |
| Descripción | Quad 2-Input NAND Gate With Open-Drain Outputs | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MC74HC03A (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 2-Input NAND Gate
With Open-Drain Outputs
High–Performance Silicon–Gate CMOS
The MC74HC03A is identical in pinout to the LS03. The device inputs
are compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a high–performance MOS
N–Channel transistor. This NAND gate can, therefore, with a suitable
pullup resistor, be used in wired–AND applications. Having the output
characteristic curves given in this data sheet, this device can be used as
an LED driver or in any other application that only requires a sinking
current.
• Output Drive Capability: 10 LSTTL Loads With Suitable Pullup Resistor
• Outputs Directly Interface to CMOS, NMOS and TTL
• High Noise Immunity Characteristic of CMOS Devices
• Operating Voltage Range: 2 to 6V
• Low Input Current: 1µA
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 28 FETs or 7 Equivalent Gates
DESIGN GUIDE
Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
* Equivalent to a two–input NAND gate
Value
7.0
1.5
5.0
0.0075
Unit
ea
ns
µW
pJ
1,4,9,12
A
2,5,10,13
B
LOGIC DIAGRAM
VCC
OUTPUT
PROTECTION
DIODE
3,6,8,11
Y*
PIN 14 = VCC
PIN 7 = GND
* Denotes open–drain outputs
MC74HC03A
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Plastic
SOIC
TSSOP
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
Z
Z
Z
L
Z = High Impedance
Pinout: 14–Lead Packages (Top View)
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
1234567
A1 B1 Y1 A2 B2 Y2 GND
10/95
© Motorola, Inc. 1995
1 REV 7
1 page  
14
1
A
F
HG
8
B
7
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
C
N
SEATING
PLANE
D
K
L
J
M
MC74HC03A
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC
2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC
7.62 BSC
M 0_ 10_ 0_ 10_
N 0.015 0.039 0.39 1.01
–A–
14
1
G
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
8
–B–
7
P 7 PL
0.25 (0.010) M B M
C R X 45°
F
SEATING
PLANE
D 14 PL
K
0.25 (0.010) M T B S
AS
M
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0° 7°
0° 7°
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet MC74HC03A.PDF ] | |
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