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PDF SH7604 Data sheet ( Hoja de datos )
| Número de pieza | SH7604 | |
| Descripción | Hardware Manual | |
| Fabricantes | Hitachi Semiconductor | |
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Hay una vista previa y un enlace de descarga de SH7604 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SH7604
Hardware Manual
ADE-602-085C
Rev. 4.0
9/19/01
Hitachi, Ltd.
1 page  
List of Items Revised or Added for This Version
Section
Page Item
Description
(see Manual for details)
1.1.1 Features of the SH7604 2 Operation Modes
Description of Clock
mode added
4 Package
176-pin plastic TFBGA
(TBP-176) added
1.3.1 Pin Arrangement
5 Product Lineup
Added
8 Figure 1.3 Pin Arrangement
(176-Pin Plastic TFBGA)
Added
1.3.2 Pin Functions
9 Table 1.1 Pin Functions
Pin No. (TBP-176) added
3.2.2 Clock Operating Mode
Setting
51
Description added
52 Table 3.3 Clock Mode Pin
Settings and States
Note 3 added
3.2.7 Notes on Board Design
61 When Using PLL Oscillation
Circuits
Description replaced
62 Figure 3.9 Design Consideration Figure amended,
When Using PLL Oscillation
additional description of
Circuits
figure
Appendix C
External Dimensions
616 Figure C.2 External Dimensions Added
(TBP-176)
5 Page 
7.7.4 Burst Access.......................................................................................................... 194
7.7.5 Refreshing ............................................................................................................. 195
7.7.6 Power-On Sequence.............................................................................................. 197
7.8 Burst ROM Interface.......................................................................................................... 197
7.9 Waits between Access Cycles............................................................................................ 200
7.10 Bus Arbitration................................................................................................................... 201
7.10.1 Master Mode ......................................................................................................... 203
7.10.2 Slave Mode ........................................................................................................... 205
7.10.3 Partial-Share Master Mode ................................................................................... 206
7.10.4 External Bus Address Monitor.............................................................................. 209
7.10.5 Master/Slave Coordination ................................................................................... 209
7.11 Other Topics....................................................................................................................... 210
7.11.1 Resets.................................................................................................................... 210
7.11.2 Access as Seen from the CPU or DMAC ............................................................. 210
7.11.3 Emulator................................................................................................................ 212
Section 8 Cache .................................................................................................................. 213
8.1 Introduction........................................................................................................................ 213
8.2 Cache Control Register (CCR) .......................................................................................... 214
8.3 Address Space and the Cache ............................................................................................ 216
8.4 Cache Operation ................................................................................................................ 216
8.4.1 Cache Reads.......................................................................................................... 216
8.4.2 Write Access ......................................................................................................... 219
8.4.3 Cache-Through Access ......................................................................................... 220
8.4.4 The TAS Instruction ............................................................................................. 221
8.4.5 Pseudo-LRU and Cache Replacement.................................................................. 222
8.4.6 Cache Initialization ............................................................................................... 224
8.4.7 Associative Purges................................................................................................ 224
8.4.8 Data Array Access ................................................................................................ 224
8.4.9 Address Array Access........................................................................................... 225
8.5 Cache Use .......................................................................................................................... 226
8.5.1 Initialization.......................................................................................................... 226
8.5.2 Purge of Specific Lines......................................................................................... 227
8.5.3 Cache Data Coherency.......................................................................................... 227
8.5.4 Two-Way Cache Mode ......................................................................................... 228
8.5.5 Usage Notes .......................................................................................................... 229
Section 9 Direct Memory Access Controller (DMAC) .......................................... 231
9.1 Overview............................................................................................................................ 231
9.1.1 Features ................................................................................................................. 231
9.1.2 Block Diagram...................................................................................................... 233
9.1.3 Pin Configuration.................................................................................................. 234
9.1.4 Register Configuration.......................................................................................... 234
v
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH7604.PDF ] | |
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