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PDF SPT7820 Data sheet ( Hoja de datos )
| Número de pieza | SPT7820 | |
| Descripción | (SPT7820 / SPT7824) EVALUATION BOARD | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FEATURES
• 20 and 40 MSPS Conversion Rate
• On-Board Clock Drivers
• Data Output and Strobe Signal
• User Selectable Capture Clock
• On-Board Reference Drivers
AN7820/24
EVALUATION BOARD
APPLICATION NOTE
APPLICATIONS
• Evaluation of SPT7820 and SPT7824
• Engineering System Prototype Aid
• Incoming Inspection Tool
• Differential Linearity Error (DLE) Testing
• Integral Linearity Error (ILE) Testing
• AC Accuracy Testing: SNR, THD
• Guide for System Layout
GENERAL DESCRIPTION
The EB7820/24 evaluation board demonstrates the perfor-
mance of the SPT7820 and SPT7824, monolithic high speed
analog-to-digital converters (ADCs). This document can
used as an application note and as supplemental information
to the existing data sheets (SPT7820 or SPT7824). Both the
SPT7820 and SPT7824 have analog input ranges of ±2 V.
The SPT7820 is capable of digitizing an analog input signal
into 10-bit words at a minimum update rate of 20 MSPS, while
the SPT7824 is capable of digitizing an analog input signal
into 10-bit words at a minimum update rate of 40 MSPS. Both
devices are pin-compatible. All input/output logic is TTL-
compatible.
Figure 1: EB7820/24 Block Diagram. (The full detail schematic is shown in figure 17.)
CLK
DGND
+2.5V
REF
+5
VIN
+ TTL
COMP
-
-5.2
CLK
VFT
-1
10
VFB Dout
VIN
AGND
-A5.2V +A5 - D5.2V
+D5V
CCLK
EB7820/24
REVB
DGND
10
10
PART OF DB792
(DAUGHTER BOARD)
12-BIT DAC
(80 MSPS MAX)
DAC
OUT
ADC OUT (TTL)
The EB7820/24 (≈ 4" X 7.5") consists of five separate sections:
- Reference circuits
- Clock circuits
- SPT7820 or SPT7824, 10-bit ADC (not included with the board)
- Output latches available through 26-pin female ribbon connector
- The DB792 DAC reconstruction board is a separate daughter board (≈ 2.5" X 3.0") that directly interfaces with the
EB7820/24
1 page  
Figure 6 - EB7820/24 Timing Diagram Where CCLK is the Same as CLK IN
Figure 7 - EB7820/24 Timing Diagram Where CCLK is 180° Out of Phase From CLK IN
U5, pin 3 N
CLK
(EB7820/24)
CLK IN
(SPT7820/24)
tpd2
tpd3
DATA OUT
(SPT7820/24)
VALID
(N-2)
CCLK
(LATCHES)
tpd1
DATA OUT
(P2)
(N-2)
N+1 N+2
tpwH
tpwL
VALID
(N-1)
ts
(N-1)
VALID
(N)
th
tpd4
(N)
N+3 N+4
VALID
(N+1)
VALID
(N+2)
(N+1)
Table 4 - P2, SPT7820/24 Output Data (Latched) , 26-Pin Female Ribbon Connector
P2 Function
Logic
P2 Function
1 CCLK
TTL 2 DGND
3 N/A
TTL/LO
4
DGND
5 N/A
TTL/LO
6
DGND
7 D0 (LSB)
TTL 8 DGND
9 D1
TTL 10 DGND
11 D2
TTL 12 DGND
13 D3
TTL 14 DGND
15 D4
TTL 16 DGND
17 D5
TTL 18 DGND
19 D6
TTL 20 DGND
21 D7
TTL 22 DGND
23 D8
TTL 24 DGND
25 D9 (MSB)
TTL 26 DGND
Logic
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
AN7820/24
5 5/22/97
5 Page 
Figure 15: Three-Bit Reconstruction DAC Waveform Using Analog Input Ramp
Ramp Input
contain n conversions
Last 3-LSB codes
111
110
101 (B)
100
011
Theoretical
010 Actual
001 (A)
Missing Code
000 (MC)
LSB Non- Monotonic DLE ≈ -1/2 LSB
(A) is the actual bit weight for the output code multiple of 011
(B) is the major transition noise. This noise level shown is greater than ± 1/2 LSB
Advantages:
Disadvantages:
1) Many tests (as stated above) can be extracted from this 1) The accuracy depends on human judgement and can be
one, simple test set-up.
very difficult if the person is not familiar with it.
2) The missing code and the transition noise can be more
accurately identified than with any other standard test
methods.
3) Set-up is quick and relatively accurate.
2) The exact code is not shown in the transfer curve, but in
a multiple of the last three bits of the LSB. To overcome
this problem, probe every bit using an oscilloscope or
install LEDs at each output (P3 connector) to signal the
state of each output bit.
AN7820/24
11 5/22/97
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet SPT7820.PDF ] | |
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