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PDF AM30LV0064D Data sheet ( Hoja de datos )
| Número de pieza | AM30LV0064D | |
| Descripción | 64 Megabit (8 M x 8-Bit) CMOS 3.0 Volt-only Flash Memory with UltraNAND Technology | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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Am30LV0064D
Data Sheet
The Am30LV0064D is not offered for new designs. Please contact your Spansion represen-
tative for alternatives.
July 2002
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 22203 Revision C Amendment +4 Issue Date October 19, 2004
1 page  
TABLE OF CONTENTS
Am30LV0064D ................................................. 1
Continuity of Specifications ...................................................... 1
Continuity of Ordering Part Numbers ....................................... 1
For More Information ................................................................ 1
This page left intentionally blank. . . . . . . . . . . . . 2
Am30LV0064D ................................................. 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions ................................................... 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Pin Description . . . . . . . . . . . . . . . . . 10
Input/Output Pins (I/O7–I/O0) ................................................. 10
Command Latch Enable (CLE) ............................................... 10
Address Latch Enable (ALE) .................................................. 10
Chip Enable (CE#) .................................................................. 10
Read Enable (RE#) ................................................................ 10
Write Enable (WE#) ................................................................ 10
Write Protect (WP#) ................................................................ 10
Spare Area Enable (SE#) ....................................................... 10
Ready/Busy Output (RY/BY#) ................................................ 10
Device Power Supply (VCC) .................................................... 10
Output Buffer Power Supply (VCCQ) ........................................ 10
Ground (VSS) .......................................................................... 10
Cell Layout And Address Assignment . . . . . . . . 11
Figure 1. Mass Storage Device Cell Layout.................................... 11
Table 1. Address Assignment .........................................................11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12
Device Bus Operations, Command Set, And
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Am30LV0064D Device Bus Operations ............................13
Table 3. Am30LV0064D Command Set ..........................................13
Table 4. Am30LV0064D Command Definitions ..............................14
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Operations .................................................................... 16
Read Data (00h / 01h) ............................................................ 16
Figure 2. Read Data........................................................................ 16
Gapless Read (02h) (Superset Command) ............................ 17
Figure 3. Gapless Read .................................................................. 17
Read Spare Area (50h) .......................................................... 18
Figure 4. Read Spare Area ............................................................. 18
Read ID (90h) ......................................................................... 19
Table 5. Am30LV0064D ID Codes ..................................................19
Figure 5. Read ID............................................................................ 19
Read Status (70h) .................................................................. 20
Figure 6. Device Status Register Bit Definition ............................... 20
Figure 7. Read Status ..................................................................... 20
Program Operations ............................................................... 20
Input Data (80h) ...................................................................... 20
Page Program (10h) ............................................................... 21
Figure 8. Input Data and Page Program ......................................... 21
Figure 9. Program Operations Flow Chart ...................................... 22
Erase Operations .................................................................... 23
Block Erase (60h) (D0h) ......................................................... 23
Figure 10. Block Erase.................................................................... 23
Erase Suspend (B0h) (Superset Command) .......................... 23
Erase Resume (D0h) (Superset Command) ........................... 23
Figure 11. Erase Suspend and Erase Resume.............................. 24
Reset Operation ..................................................................... 25
Reset (FFh) ............................................................................. 25
Figure 12. Reset............................................................................. 25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26
Figure 13. Maximum Negative Overshoot Waveform .................... 26
Figure 14. Maximum Positive Overshoot Waveform...................... 26
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 26
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. Test Specifications ........................................................... 27
Figure 15. Test Setup..................................................................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Command, Data, and Address Input ...................................... 28
Normal Operation ................................................................... 28
Mode Selection ....................................................................... 29
Key To Switching Waveforms . . . . . . . . . . . . . . . 29
Figure 16. Command Input Cycle .................................................. 30
Figure 17. Address Input Cycle...................................................... 30
Figure 18. Data Input Cycle ........................................................... 31
Figure 19. Serial Read Cycle ......................................................... 31
Figure 20. Status Read Cycle ........................................................ 32
Figure 21. Read Data..................................................................... 32
Figure 22. Read Data (Interrupted by CE#) ................................... 33
Figure 23. Read Spare Area .......................................................... 33
Figure 24. Sequential Read ........................................................... 34
Figure 25. Page Program............................................................... 34
Figure 26. Block Erase................................................................... 35
Figure 27. Erase Suspend ............................................................. 35
Figure 28. Erase Resume .............................................................. 36
Figure 29. Sequential Page Program............................................. 36
Figure 30. ID and Manufacturer Read............................................ 37
Figure 31. Write Protect (WP#) Timing During Power Transitions. 37
Program And Erase Characteristics . . . . . . . . . 38
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 38
TSOP II Pin Capacitance . . . . . . . . . . . . . . . . . . . 38
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39
TS 044—44/40-Pin Standard Thin Small Outline Package II . 39
TSR044—44/40-Pin Reverse Thin Small Outline Package II . 40
FBE040—40-Ball Fine Pitch Ball Grid Array (FBGA)
8 x 15 mm package ................................................................ 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision A (December 1998) .................................................. 42
Revision B (December 1998) .................................................. 42
Revision B+1 (January 1999) ................................................. 42
Revision B+2 (February 1999) ................................................ 43
Revision B+3 (March 8, 1999) ................................................ 43
Revision B+4 (April 21, 1999) ................................................. 43
Revision B+5 (June 17, 1999) ................................................ 43
Revision C (May 19, 2000) ..................................................... 43
Revision C+1 (June 23, 2000) ................................................ 43
Revision C+2 (August 14, 2000) ............................................. 43
Revision C+3 (October 6, 2000) ............................................. 43
Am30LV0064D
5
5 Page 
CELL LAYOUT AND ADDRESS ASSIGNMENT
512 + 16 Byte
Data Register
256 256 16
Flash Memory
Array
16,384 Pages
(1,024 Blocks)
I/O 0
~
I/O 7
16 Pages
(1 Block)
528 Bytes
(1 Page)
Note: Device programming is executed on a page basis while erase is performed on a block basis. During read operations, data
is transferred from the Flash array to the internal Data Register on a page basis. Data is then sequentially read from the Data
Register on a Byte basis.
Figure 1. Mass Storage Device Cell Layout
Table 1. Address Assignment
First Cycle
Second Cycle
Third Cycle
I/O 7
A7
A16
X
I/O 6
A6
A15
X
I/O 5
A5
A14
A22
I/O 4
A4
A13
A21
I/O 3
A3
A12
A20
I/O 2
A2
A11
A19
I/O 1
A1
A10
A18
I/O 0
A0
A9
A17
Legend:
Axx = specific address bit, X = don’t care (VIH or VIL)
Notes:
1. A8 is automatically set “Low” or “High” by the 00h or 01h command.
2. A22 to A13 specifies the Block Address, A12 to A9 specifies the Page Address within a block, and A7 to A0 identifies the
byte address within half a page.
Am30LV0064D
11
11 Page | ||
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| PDF Descargar | [ Datasheet AM30LV0064D.PDF ] | |
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