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Número de pieza | MC68340 | |
Descripción | Integrated Processor Unit | |
Fabricantes | Motorola Semiconductors | |
Logotipo | ||
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Freescale Semiconductor, Inc.
µ MOTOROLA
MC68340
Integrated Processor with DMA
User’s Manual
©MOTOROLA INC., 1992
For More Information On This Product,
Go to: www.freescale.com
1 page 11/2/95
FreSEeCsTcIOaNle1:SOeVmERicVoIEnWductor, Inc. UM Rev.1.0
TABLE OF CONTENTS (Continued)
Paragraph
Number
Title
Page
Number
2.7
2.7.1
2.7.2
2.7.3
2.7.4
2.7.5
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.9
2.9.1
2.9.2
2.9.3
2.10
2.10.1
2.10.2
2.10.3
2.10.4
2.11
2.11.1
2.11.2
2.11.3
2.11.4
2.12
2.12.1
2.12.2
2.12.3
2.13
2.13.1
2.13.2
2.13.3
2.13.4
2.13.5
2.13.6
2.13.7
2.13.8
2.14
2.14.1
2.14.2
2.14.3
Bus Control Signals .........................................................................................2-6
Data and Size Acknowledge (DSACK1, DSACK0)................................2-6
Address Strobe (AS)....................................................................................2-6
Data Strobe (DS)...........................................................................................2-7
Transfer Size (SIZ1, SIZ0) ..........................................................................2-7
Read/Write (R/W)...........................................................................................2-7
Bus Arbitration Signals....................................................................................2-7
Bus Request (BR)..........................................................................................2-7
Bus Grant (BG)...............................................................................................2-7
Bus Grant Acknowledge (BGACK).............................................................2-7
Read-Modify-Write Cycle (RMC).................................................................2-8
Exception Control Signals ..............................................................................2-8
Reset (RESET)...............................................................................................2-8
Halt (HALT)....................................................................................................2-8
Bus Error (BERR)...........................................................................................2-8
Clock Signals ....................................................................................................2-8
System Clock (CLKOUT)............................................................................2-8
Crystal Oscillator (EXTAL, XTAL)...............................................................2-9
External Filter Capacitor (XFC) ..................................................................2-9
Clock Mode Select (MODCK).....................................................................2-9
Instrumentation and Emulation Signals .......................................................2-9
Instruction Fetch (IFETCH)..........................................................................2-9
Instruction Pipe (IPIPE)...............................................................................2-9
Breakpoint (BKPT)........................................................................................2-10
Freeze (FREEZE)..........................................................................................2-10
DMA Module Signals.......................................................................................2-10
DMA Request (DREQ2, DREQ1).................................................................2-10
DMA Acknowledge (DACK2, DACK1)......................................................2-10
DMA Done (DONE2, DONE1)......................................................................2-10
Serial Module Signals.....................................................................................2-11
Serial Crystal Oscillator (X2, X1) ...............................................................2-11
Serial External Clock Input (SCLK)...........................................................2-11
Receive Data (RxDA, RxDB).......................................................................2-11
Transmit Data (TxDA, TxDB).......................................................................2-11
Clear to Send (CTSA, CTSB).....................................................................2-11
Request to Send (RTSA, RTSB)................................................................2-11
Transmitter Ready (T≈RDYA).....................................................................2-11
Receiver Ready (R≈RDYA) .........................................................................2-12
Timer Signals ....................................................................................................2-12
Timer Gate (TGATE2, TGATE1)................................................................2-12
Timer Input (TIN2, TIN1) ..............................................................................2-12
Timer Output (TOUT2, TOUT1)...................................................................2-12
iv
MC68340 USER'S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
5 Page 11/2/95
FreSEeCsTcIOaNle1:SOeVmERicVoIEnWductor, Inc. UM Rev.1.0
TABLE OF CONTENTS (Continued)
Paragraph
Number
Title
Page
Number
5.6.1.3
5.6.2
5.6.2.1
5.6.2.2
5.6.2.2.1
5.6.2.2.2
5.6.2.2.3
5.6.2.3
5.6.2.4
5.6.2.5
5.6.2.5.1
5.6.2.5.2
5.6.2.5.3
5.6.2.6
5.6.2.7
5.6.2.7.1
5.6.2.7.2
5.6.2.8
5.6.2.8.1
5.6.2.8.2
5.6.2.8.3
5.6.2.8.4
5.6.2.8.5
5.6.2.8.6
5.6.2.8.7
5.6.2.8.8
5.6.2.8.9
5.6.2.8.10
5.6.2.8.11
5.6.2.8.12
5.6.2.8.13
5.6.2.8.14
5.6.2.8.15
5.6.2.8.16
5.6.3
5.6.3.1
5.6.3.2
5.6.3.3
5.7
5.7.1
5.7.1.1
5.7.1.2
On-Chip Hardware Breakpoint Overview.............................................5-64
Background Debug Mode...........................................................................5-65
Enabling BDM ...........................................................................................5-65
BDM Sources ............................................................................................5-66
External BKPT Signal..........................................................................5-66
BGND Instruction ..................................................................................5-66
Double Bus Fault. .................................................................................5-66
Entering BDM ............................................................................................5-66
Command Execution................................................................................5-67
BDM Registers...........................................................................................5-67
Fault Address Register (FAR) .............................................................5-67
Return Program Counter (RPC) .........................................................5-67
Current Instruction Program Counter (PCC)....................................5-67
Returning from BDM.................................................................................5-68
Serial Interface..........................................................................................5-68
CPU Serial Logic..................................................................................5-69
Development System Serial Logic....................................................5-71
Command Set ...........................................................................................5-73
Command Format.................................................................................5-73
Command Sequence Diagram..........................................................5-74
Command Set Summary.....................................................................5-75
Read A/D Register (RAREG/RDREG)................................................5-76
Write A/D Register (WAREG/WDREG) ..............................................5-77
Read System Register (RSREG)........................................................5-77
Write System Register (WSREG).......................................................5-78
Read Memory Location (READ).........................................................5-79
Write Memory Location (WRITE)........................................................5-79
Dump Memory Block (DUMP). ...........................................................5-80
Fill Memory Block (FILL)......................................................................5-82
Resume Execution (GO)......................................................................5-83
Call User Code (CALL)........................................................................5-83
Reset Peripherals (RST)......................................................................5-85
No Operation (NOP).............................................................................5-85
Future Commands................................................................................5-86
Deterministic Opcode Tracking..................................................................5-86
Instruction Fetch (IFETCH)......................................................................5-86
Instruction Pipe (IPIPE)...........................................................................5-87
Opcode Tracking during Loop Mode ....................................................5-88
Instruction Execution Timing...........................................................................5-88
Resource Scheduling ..................................................................................5-88
Microsequencer ........................................................................................5-89
Instruction Pipeline...................................................................................5-89
x
MC68340 USER'S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet MC68340.PDF ] |
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