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PDF SST49LF040 Data sheet ( Hoja de datos )
| Número de pieza | SST49LF040 | |
| Descripción | 4 Mbit LPC Flash | |
| Fabricantes | Silicon Storage Technology | |
| Logotipo |  |
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4 Mbit LPC Flash
SST49LF040
FEATURES:
SST49LF0404 Mb LPC Flash
Advance Information
• LPC Interface Flash
– SST49LF040: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification 1.0
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– 64 KByte Top boot block protection
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Low Pin Count (LPC) Interface mode for
in-system operation
– Parallel Programming (PP) mode for fast production
programming
• LPC Interface Mode
– 5-signal communication interface supporting
byte Read and Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write protect
for entire chip and/or top boot block
– Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– ID pins for multi-chip selection
– Decode both top and bottom regions of the
system memory map
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast programming In-System on pro-
grammer equipment
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST49LF040 flash memory devices are designed to
interface with the LPC bus for PC and Internet Appliance
application in compliance with Intel Low Pin Count (LPC)
Interface Specification 1.0. Two interface modes are sup-
ported by the SST49LF040: LPC mode for In-System
operation and Parallel Programming (PP) mode to interface
with programmer equipment.
The SST49LF040 flash memory devices are manufactured
with SST’s proprietary, high performance SuperFlash Tech-
nology. The split-gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability com-
pared with alternate approaches. The SST49LF040 device
significantly improves performance and reliability, while low-
ering power consumption. The SST49LF040 device writes
(Program or Erase) with a single 3.0-3.6V power supply. It
uses less energy during Erase and Program than alterna-
tive flash memory technologies. The total energy con-
sumed is a function of the applied voltage, current and time
of application. Since for any give voltage range, the Super-
Flash technology uses less current to program and has a
shorter erase time, the total energy consumed during any
Erase or Program operation is less than alternative flash
memory technologies. The SST49LF040 product provides
a maximum Byte-Program time of 20 µsec. The entire
memory can be erased and programmed byte-by-byte typ-
ically in 8 seconds when using status detection features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of Program operation. The SuperFlash technology pro-
vides fixed Erase and Program time, independent of the
number of Erase/Program cycles that have performed.
Therefore the system software or hardware does not have
to be calibrated or correlated to the cumulative number of
erase cycles as is necessary with alternative flash memory
technologies, whose Erase and Program time increase
with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST49LF040 device is offered in 32-lead TSOP and 32-
lead PLCC packages. See Figures 2 and 3 for pin assign-
ments and Table 1 for pin descriptions.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01
562
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.
1 page  
4 Mbit LPC Flash
SST49LF040
Advance Information
LIST OF TABLES
TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 2: ID Strapping Values for SST49LF040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
TABLE 3: General Purpose Inputs Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 4: Memory Map Register Addresses (Top of the 4GB System Memory). . . . . . . . . . . . . . . . . . . . 13
TABLE 5: Memory Map Register Addresses (Bottom of the 4GB System Memory) . . . . . . . . . . . . . . . . . 13
TABLE 6: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 7: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 8: Software Command Sequence (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TABLE 9: DC Operating Characteristics (All Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 10: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 11: Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 12: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 13: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TABLE 14: Reset Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TABLE 15: Read/Write Cycle Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TABLE 16: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TABLE 17: Interface Measurement Condition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 18: Standard LPC Memory Cycle Definition (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 19: Read Cycle Timing Parameters (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 20: Program/Erase Cycle Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TABLE 21: Reset Timing Parameters (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
©2001 Silicon Storage Technology, Inc.
5
S71213-00-000 11/01 562
5 Page 
4 Mbit LPC Flash
SST49LF040
Advance Information
With hardware strapping, ID bits in the address field is
included in every LPC address memory cycle. The address
bits [A22: A19] are used to select the device with proper
IDs. The ID strapping bits in the address field will be
decoded depending on where the device is mapped on the
4 GByte system memory map. See Table 2 for ID address
bits decoding. The device will compare these bits with
ID[3:0]’s strapping values. If there is a mismatch, the device
will ignore the remainder of the cycle.
TABLE 2: ID STRAPPING VALUES FOR SST49LF040
Hardware
Strapping
Address Bits [A22-A19]
Decoding1
4 GByte System Memory
Device #
ID[3:0]
Top
Bottom
0 (Boot device) 0000
1111b
0001b
1
0001
1110b
0000b
2
0010
1101b
0011b
3
0011
1100b
0010b
4
0100
1011b
0101b
5
0101
1010b
0100b
6
0110
1001b
0111b
7
0111
1000b
0110b
8
1000
0111b
1001b
9
1001
0110b
1000b
10
1010
0101b
1011b
11
1011
0100b
1010b
12
1100
0011b
1101b
13
1101
0010b
1100b
14
1110
0001b
1111b
15
1111
0000b
1110b
T2.3 562
1. Address bits A22-A19 decoding for multiple device selection
depends on whether the device is mapped from the top of the
4GB system memory map or from the bottom of the 4GB
system memory map.
(Boot Block)
Boot Device #0
(Boot Block)
Device #1
(Boot Block)
Device #2
(Boot Block)
Device #3
FFFF FFFFH
8 MByte
Memory Access
(Boot Block)
Device #14
(Boot Block)
Device #15
Device #0
FF80 0000H
FF7F FFFFH
Device #1
Device #2
Device #3
8 MByte
Register Access
Device #14
Device #15
562 ILL F01.1
FF00 0000H
FIGURE 4: BOOT CONFIGURATION FROM THE TOP
OF THE 4 GBYTE SYSTEM MEMORY MAP
©2001 Silicon Storage Technology, Inc.
11
S71213-00-000 11/01 562
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST49LF040.PDF ] | |
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